An automatic gain control architecture for SONET OC-3 VLSI

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Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/29290

Title:	An automatic gain control architecture for SONET OC-3 VLSI
Authors:	Wang,CK;Huang,PC
Contributors:	電機工程研究所
Date:	1997
Issue Date:	2010-06-29 20:20:59 (UTC+8)
Publisher:	中央大學
Abstract:	This brief presents a synchronized feedback-type automatic gain control (AGC) architecture for SONET (synchronous optical network) OC-3 system which is suitable for scaled BJT or CMOS VLSI implementation, In this architecture, a second-order loop is utilized instead of a conventional loop, and a convenient methodology is presented for calculating the parameters of the AGC. Simulation results using micromodels in the HSPICE environment indicate that for a 20 dB dynamic range of input 77.76 MHz sinusoidal signal, the architecture yields an 80 kHz loop bandwidth and a constant 1 V-pp output magnitude.
Relation:	IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING
Appears in Collections:	[Graduate Institute of Electrical Engineering] journal & Dissertation

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