氫等離子體吸附成核、聚核、成膜分離矽奈米薄膜現象之研究; Study of Nucleation, Mergence, Growth of Gas Film by Hydrogen Plasma to Split Nano-Scale Layer from Substrate

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题名:	氫等離子體吸附成核、聚核、成膜分離矽奈米薄膜現象之研究;Study of Nucleation, Mergence, Growth of Gas Film by Hydrogen Plasma to Split Nano-Scale Layer from Substrate
作者:	巫秉融;Ping-Jung Wu
贡献者:	機械工程研究所
关键词:	絕緣層上覆矽;電漿浸沒式離子佈植;silicon on insulator;plasma immersion ion implantation
日期:	2008-06-11
上传时间:	2009-09-21 12:07:30 (UTC+8)
出版者:	國立中央大學圖書館
摘要:	本研究探討以氫電漿浸沒式離子佈植技術取代智切法Smart-cut®製程中傳統氫離子佈植技術的可能性。氫電漿浸沒式離子佈植技術相較於傳統氫離子佈植，具有佈植面積大、效率高、低成本的優勢。智切法中的氫離子佈植製程透過質譜儀篩選出單一種類離子，再將其加速注入基板的特定深度，藉以定義薄膜分離位置。但氫電漿浸沒式離子佈植系統中排除了質譜儀的使用，雖然大幅降低機台成本，在佈植過程中卻會同時植入H+、H2+、H3+三種不同的氫離子，在加速能量相同，荷/質比卻不同的情況下，在矽塊材的表面形成分布廣泛的氫離子佈植區域，無法定義出明確的薄膜分離位置。我們為了維持氫電漿浸沒式離子佈植技術既有的低成本優勢，在不加裝質譜儀前提下，試圖以特殊設計的異質基板結構，解決氫電漿浸沒式離子佈植技術中，由於分布廣泛的氫離子佈植區域而無法定義出明確的薄膜分離位置的問題；同時藉由特定元素的導入，試圖將智切法製程中，薄膜分離時所需的450°C熱處理溫度降低至250°C之下。換言之，本研究成果可藉由特殊的嵌入式異質結構明確定義轉移薄膜的厚度，並降低製程所需的熱處理溫度。不同於傳統智切法製程中以氫離子佈植能量決定欲轉移之薄膜的厚度，本研究為100奈米以下的絕緣層上矽基板製作方式提供一項創新的技術。 This research investigates the feasibility of the hydrogen plasma immersion ion implantation system (PIII) replacing the conventional ion implantation step in Smart-cut process. PIII system offers several advantages such as large implanted area, high throughput, and low cost as compared with conventional ion implantation. The hydrogen ion implantation in Smart-cut process selects specific hydrogen ions by extraction system and then accelerates it to implant into the specific depth at certain implant energy for layer splitting. Although there is no extraction implement in hydrogen PIII system for low cost, a large distribution area is formed by three ions with same implanted energy but different charge/mass, H+, H2+, and H3+. The surface roughness of transferred layer increases due to unapparent layer splitting position. A special heterostructure substrate was designed and combined with low cost hydrogen PIII without extraction system to solve this problem. Moreover, the insertion of an extra element let us decrease the annealing temperature for layer splitting to 250°C in contrast to the temperature used in Smart-cut process, 450°C. In other words, this research achievement can define the thickness of transferred layer and reduce the annealing temperature as a result of the special inserted heterostructure. This research supplies an innovative technique different from conventional Smart-cut process for the top layer of silicon on insulator fabrication less than 100nm thickness.
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