A Multi-Code Compression Scheme for Test Time Reduction of System-on-Chip Designs

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Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/31764

Title:	A Multi-Code Compression Scheme for Test Time Reduction of System-on-Chip Designs
Authors:	Shieh,Hong-Ming;Li,Jin-Fu
Contributors:	電機工程研究所
Date:	2008
Issue Date:	2010-07-06 18:11:05 (UTC+8)
Publisher:	中央大學
Abstract:	With the nano-scale technology. an system-on-chip (SOC) design may consist of many reusable cores front multiple sources. This causes that the complexity of SOC testing is much higher than that of conventional VLSI chip testing. One of the SOC test challe
Relation:	IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS????
Appears in Collections:	[Graduate Institute of Electrical Engineering] journal & Dissertation

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