利用平行處理架構之 CRC 網路封包錯誤更正器研製 ; The Design and Implementation of CRC Based Packet Error Corrector Using Parallel Architecture

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Title:	利用平行處理架構之 CRC 網路封包錯誤更正器研製;The Design and Implementation of CRC Based Packet Error Corrector Using Parallel Architecture
Authors:	歐亭鎔;Ting-rong Ou
Contributors:	通訊工程研究所
Keywords:	封包錯誤更正;CRC
Date:	2010-07-26
Issue Date:	2010-12-09 13:46:30 (UTC+8)
Publisher:	國立中央大學
Abstract:	現今的網路模型中的媒體存取控制（Medium Access Control - MAC）層使用 CRC-32 的編碼方式，先對原始資料進行編碼之後封裝為資料訊框再進行傳輸。當接收端收到資料訊框後，會計算此訊框的 CRC-32 餘數以檢查所接收到的訊框是否正確。如果 CRC-32 檢測訊框有錯誤，接收端的 MAC 層會使用 ARQ（Automatic Repeat reQuest）協定進行訊框的重傳，以期待再次的重傳可以收到正確的訊框。 ARQ 詳細的運作機制如下，當傳送端送出訊框後，會等待接收端對這個訊框回應一個「確認收到(acknowledge, ACK)」的訊息。如果經過一段時間傳送端沒有收到 ACK（稱之為 timeout），很可能接收端沒有收到該訊框或收到有錯的訊框（經由 CRC-32 檢查機制），這時傳送端就會重傳此訊框，以期待再次的重傳可以成功。 ARQ protocol 使得訊框得以在不可靠的通訊通道中提供可靠的通訊。從資訊理論的角度可以發現一個位元的錯誤會造成整個資料訊框的錯誤與重送。因此，如果能適當儲存之前發生錯誤的原始訊框資料，並比對重送但仍發生錯誤之訊框資料，有相當大的機會可以找出正確的原始訊框資料，也因此達到 MAC 層支援錯誤修正之能力。延續我們先前所研發的 CRC 網路封包錯誤更正器[1]，本論文進一步利用平行架構來實作 CRC 網路封包錯誤更正器以減低電路複雜度以及所花費的時間。Usually, data frames encapsulated in the medium access control MAC layer are protected by the well-known CRC-32 mechanism. The CRC-32 redundant information is produced by encoding the original data according to a pre-specified polynomial function. Upon the receiver receiving the data frame, it calculates the CRC-32 remainder of the received frame for determining whether the received data frame is correct or not. If the checking fails, the automatic repeat request (ARQ) protocol of MAC layer will be triggered to retransmit the erroneous data frame from transmitter to receiver. ARQ protocol is designed to achieve reliable transmissions over unreliable channel, and thus the packet loss probability is decreased. However, there is an issue that one erroneous data bit in a data frame will cause whole data frame to be retransmitted. This thesis proposes to properly store erroneous data frame(s) and combine it with the newly retransmitted frame may find out the original data frame. Based on our preliminary work [1], this thesis further utilizes the parallel architecture to construct the CRC based packet error corrector, which has the features of low circuit complexity and short processing time, as compared to the previously developed serial CRC based packet error corrector (CEC).
Appears in Collections:	[Graduate Institute of Communication Engineering] Electronic Thesis & Dissertation

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