本論文利用電阻串陣列來排列探討空間相關性與元件分段其抑制非線性誤差的能力，而隨著改變排列所造成在實體佈局上繞線困難度增加，且導線阻值不一致會增加系統失誤，增加積分非線性誤差。利用本論文提出佈局上平衡導線通道繞線法的四個準則：相同的via 個數、垂直方向的金屬層阻值相同且水平方向的金屬層阻值相同、最佳聯線路徑、依導線長度調整其寬度，便能在同位元不同排列下，平衡所有導線寄生阻值。在四位元探戈行軍式螺旋排法，導線寬1.42μm 使用平衡導線通道繞線法，可以將整體導線阻值的均方根誤差從1.89Ω減少到0Ω。This paper discusses the suppression capability of INL with the concept of spatial correlation and segment method in the resistor-string array. In physical layout, permutation may cause the difficulty in routing, systematic error like unbalanced channel resistance increases the INL. This paper proposes four rules on physical routing called Balanced Interconnect Channel Routing (BICR), adjusting the channel width follow the channel length, choosing the same via numbers, the metal resistances of vertical direction are the same and the metal resistances of horizontal direction are the same too, and optimizing the path of interconnection to balance the parasitic resistances in all channel under different permutation of the same resolution. In 4bits Snake sequence of Tango Route March, the root-mean-square value of parasitic resistance can be reduced from 1.89 ohm to zero ohm by BICR when the width of metal line in interconnect is 1.42um.
