內嵌式記憶體的良率將大大影響著整體SOC 晶片的良率。如何有效提昇記憶體之良率已經成為SOC 設計者所面臨的一大挑戰。記憶體自我修復技術近年來已廣泛被使用來測試與修復內嵌式記憶體。然而，在現今SOC 中有許多特殊記憶體需要新的自我修復技術，才能有效的提昇這些記憶體之良率。另外，在系統層級來看，SOC 中這麼多的記憶體應如何以最短的時間作最有效的修復是一個非常困難的問題。此計畫將在第一年，針對特殊記憶體（多埠記憶體、休眠式記憶體）開發自我修復技術及針對有動態瑕疵之記憶體開發可容忍動態瑕疵之自我修復技術。第二年，將著重於解決系統層級之自我修復技術之整合。另外，為了減少測試與修復時間，我們將開發平行修復技術與低測試機台佔用時間之自我修復技術。第三年，將著重於把前兩年開發之技術整合並完成自我修復自動化設計平台。 The yield of a system-on-chip (SOC) is dominated by the yield of the memory cores in the chip. Therefore, how to enhance the yield of memory cores is one big challenge for the SOC designer. Although memory built-in self-repair (BISR) techniques have widely used to enhance the yield of memory cores, new BISR techniques still are required for efficiently repairing specific memories (e.g., multiport RAMs, drowsy RAMs, etc.) . In the system point of view, it is very difficult to test and repair so many memory cores in an SOC in very short time. In this project, we will develop new BISR techniques for specific memories (multiport RAMs and drowsy RAMs) and for memories with dynamic faults in the first year. In the second year, we will develop the integration techniques for BISR circuits in an SOC. Also, we will develop parallel BISR techniques for multiple RAMs and low tester occupation time BISR schemes to reduce the test and repair time. In the third year, we will implement an automation platform for generating the BISR designs developed in the first and second years. 研究期間：9908 ~ 10007
