隨著積體電路製程技術進入到奈米（nanometer）的時代，電源完整性（power integrity）變成一項重要的議題。同步切換雜訊（simultaneous switching noise）是電源供應雜訊（power supply noise）的一個重要部份，隨著電路時脈速度和總電流密度的增加，同步切換雜訊會造成更嚴重的電源電壓變動。傳統上，要等到電晶體層級（transistor level）的模擬才能得知同步切換雜訊的大小，但對於複雜電路而言，其模擬的時間非常久，所以本篇論文提出了一個在閘級層（gate level）估測動態同步切換雜訊的方法。考慮電源雜訊的影響，由先進標準元件庫（standard cell library）得到的理想電源電流波形（supply current waveform），經由RLC低通濾波器轉換可得到修正的電流，利用此修正電流，就可藉由基本的電感公式求出同步切換雜訊。由於所需的資料皆可在閘級層得到，所以可以快速地得到估測結果。實驗結果顯示，我們所提出的電流修正方法可以明顯地改善電源雜訊估測的精準度，因此可幫助使用者在電路設計初期做初步的雜訊估測。 As the integrated circuit process technology goes into the nanometer era, power integrity becomes an important issue. Simultaneous switching noise is a major component of the power supply noise. Due to the increased clock rate and current density, this noise would result in more serious voltage fluctuations in power network. Traditionally, the simultaneous switching noise can be analyzed by the transistor-level simulation only, which takes too much simulation time for complex circuits. Thus, this thesis proposes a method of estimating the dynamic simultaneous switching noise at gate level. In order to consider the power supply noise effects, the ideal supply current waveform obtained from the standard cell library is modified by a RLC low-pass filter transformation. With the modified current waveform, the simultaneous switching noise can be derived easily by using the basic formula of inductor. Because all the required input data of this method can be obtained at gate level, the estimation is very quick. The experimental results show that the accuracy of the estimation results can be significantly improved by the proposed approach. It can help users to do the preliminary noise estimation at early design stage.
