應用在DDR4動態隨機存取記憶體之低時脈 抖動延遲鎖定迴路 ; A Low Jitter Delay-Locked-Loop Applied on DDR4 DRAM

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題名:	應用在DDR4動態隨機存取記憶體之低時脈抖動延遲鎖定迴路;A Low Jitter Delay-Locked-Loop Applied on DDR4 DRAM
作者:	魏湘云;Hsiang-Yun Wei
貢獻者:	電機工程研究所碩士在職專班
關鍵詞:	延遲鎖定迴路;電流幫浦;低抖動;low jitter;Delay-locked-loop;charge pump
日期:	2011-08-09
上傳時間:	2012-01-05 14:58:23 (UTC+8)
摘要:	此論文是基於對穩定且低抖動的內嵌式同步電路晶片的需求而生。隨著CMOS製程技術的進步與突破，電子產品的操作頻率一再提升，其中所使用到的記憶體的複雜度及時脈訊號頻率均迅速增加，因此，系統內部同步時脈訊號之可靠度便愈來愈重要。目前動態隨機存取記憶體( Dynamic Random Access Memory )已發展至DDR4的階段，時脈速度升高至1.6Gbps~3.2Gbps，在此高速的操作下，時脈穩定成為一個必需的設計重點，由於在時脈抖動及回路穩定性上，延遲鎖定迴路（Delay-locked loop）都具有良好的表現，使得延遲鎖定迴路比鎖相迴路（Phase-locked loop）更廣泛地應用在記憶體的時脈誤差調整電路上。在本論文中提出一個具備電流匹配的電流幫浦及晶片內建電源穩壓器的延遲鎖定迴路，電路使用TSMC 90nm 1P/9M CMOS製程實現晶片，工作電壓在1.2V及I/O 2.5V，延遲鎖定迴路的輸入參考頻率為1.6GHz，在靜電源供應下最大時脈抖動（peak to peak jitter）為1.68ps ，而在有10MHz、+/-10%電壓振幅的隨機雜訊干擾下的電源供應，經過穩壓器後的時脈抖動為18.68ps，小於輸出時脈週期的2.9%，延遲迴路本身功率消耗為20.58mW，晶片面積為0.5625mm2。 Abstract The motivation of this work is the demand for a stable and low-jitter synchronous circuit on intra-chip. The operation frequencies of electronic products constantly increase along with the development and breakthrough of the CMOS process technology. The complexity of design and frequency of clock in memory has also been rapidly increasing. Thus, the reliability of synchronous circuits becomes more and more essential. Dynamic Random Access Memory (DRAM) has progressed to DDR4, reaches data rate 1.6Gbps~3.2Gbps. The stability of clock becomes an essential part of design. The delay-locked loop (DLL) offers better jitter and stability performance than the phase-locked loop (PLL). So, it is more regularly applied on DRAM as a synchronous circuit than PLL. This work presents a technique that includes a current-matching charge pump and an on-chip supply regulator in the delay-locked loop (DLL). The design is implemented by TSMC CMOS 1P/9M 90nm technology with a nominal supply voltage 1.2V and I/O supply voltage 2.5V. The input frequency is at 1.6GHz. Peak to peak jitter 1.68ps with a quiet supply, and 18.68ps under random noise of 10MHz, +/-10% amplitude on the supply after regulator, which is less than 11.5% of output clock cycle. DLL power dissipation is 20.58mW. Chip area is 0.5625mm2.
顯示於類別:	[電機工程學系碩士在職專班] 博碩士論文

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