| 摘要: | 本計劃分成三年來研究發展無線高畫質影音傳輸系統(Wireless High Definition Media Transmission System)之超外差式(heterodyne)毫米波V-頻段收發機之各關鍵電路與整合系統。為期三年計劃將達成應用於Wireless HD 系統之毫米波V-頻段收發機整合系統晶片(SoC)的驗證，其收發機架構依信號傳收之途徑，可區分為接收器、發射器及鎖相迴路系統。接收器之主要組成電路為低雜訊放大器、降頻混頻器與本地振盪源；發射鏈路主要為功率放大器、推動放大器、升頻混頻器；頻率合成器次系統電路包含 Sampling 混頻器、低通濾波器、壓控振盪器以及除頻器；天線系統方面則包含多重輸入輸出陣列天線、切換開關以及帶通濾波器。以上電路將使用國家晶片中心(CIC)經由國內台積電(TSMC)公司所提供之90-nm 金氧半場效高電子遷移率電晶體來實現完成。第一年將發展達靈頓對(Darlington pairs)基礎電路，並完成其等效電路之理論推導與設計準則；然後，將其應用在各個毫米波子電路中，使單顆電晶體之截止頻率fT 成倍頻延伸，進而改善其電路特性，同時不受元件之製程限制，充分使CMOS 元件在毫米波頻段得到足夠增益及低功率損耗；第二年為研製V-頻段毫米波鎖相迴路(PLL)模組，設計其子電路架構並整合成一個完整的頻率合成器次系統模組；第三年為建構適用於各收發端電路之慢波薄膜微帶線(slow wave thin film microstrip line; S-TFML)模型藉以達到實際縮小晶片面積之目的。再者，整合佈局前兩年完成的各個子電路，進而完成應用於 V-頻段之發射機、接收機與頻率合成器三個毫米波系統晶片模組，其中將考量電路最佳化佈局以降低雜訊干擾、電路串接級間匹配、電路相鄰交互偶合效應，與高頻直流偏壓及旁路電容處理。 This three-year project is primarily targeted to study the key components for V-band millimeter wave transceiver using Darlington pair technology. In the first year, we dedicate to design the Darlington pairs for each V-band functional circuit using TSMC 90-nm CMOS technology. The equivalent circuit analysis will be first derived, and the design criteria using Darlington pairs for LNA, VCO, and mixer circuits will be extensively investigated. The Darlington pair is demonstrated, especially in its power gain performance, to have better fT and fmax than those in the single transistor. Since the power gain is so treasure in mm-wave frequency, the proposed Darlington pair circuits provides much better design margin to implement the functional circuits, such as LNA, mixer, and VCO in mm-wave frequency regime. In the 2nd year project, we will study the phase lock loop (PLL) system for V-band operation. The on-chip antenna and band-pass filter will be also designed in the second year. In the 3rd year project, we will measure the designed circuits and devising the S-TFML (slow wave thin film micro-strip line) model for each V-band circuit. Besides, we also will start to integrate the transmitter, receiver and PLL into a compact size system-on-a-chip (SoC), respectively. The transceivers include a Darlington low noise amplifier (LNA), a drive amplifier (DA), a medium power amplifier (PA), two Darlington up/down mixers, a Darlington voltage control oscillator (VCO), a Darlington divider and phase-locked loop (PLL). The antenna system is combined with on-chip antenna array, switch and band-pass filter. The designed circuits are fabricated in TSMC 90-nm CMOS technology 研究期間：10008 ~ 10107 |
