| 摘要: | 使用矽穿孔（through silicon via, TSV）之三維整合技術已經被認為是用來克服現今二維技術所面臨挑戰之好方法。一顆三維積體電路（3D IC）以多顆晶粒堆疊起來且晶粒與晶粒間使用矽穿孔作為垂直連接線。如此可以使得在二維積體電路（2D IC）中之長導線若在3D IC 中實現，其導線長度可以大大降低，進而大幅提昇電路性能及降低功率消耗。更進一步的是，利用TSV 做訊號傳輸使的其可用之IO 個數遠超過2D IC 之IO pad 個數，因此其資料傳輸頻寬可以大幅提昇。除上述特色之外，與2D IC 相比3D IC 還有許多優點，如：高功能性（適合異質整合）、低功率、小外觀尺寸等。但是，在3D IC 可以進入量產之前，還有許多設計、電子設計自動化及測試相關挑戰須被克服。為了克服這些挑戰，開發有效的設計、電子設計自動化及測試之關鍵技術是絕對必要的。因此，本計畫提案結合有混合訊號電路設計、電子設計自動化及測試專家試圖研發這些關鍵技術。本整合型計畫共包含總計畫及四個子計畫，其名稱如下：總計畫﹕應用於三維積體電路之設計、自動化與測試關鍵技術子計畫一﹕應用於三維積體電路之晶粒間介面技術子計畫二﹕應用於三維積體電路之異質系統探索平台與電源規劃技術子計畫三﹕應用於三維積體電路之效能導向實體設計自動化子計畫四﹕應用於三維積體電路之可測性設計技術與自動化 Three-dimensional (3D) integration using through silicon via (TSV) has been proposed as a very good alternative to cope with the challenges faced by the current 2D technology. A 3D IC using TSV is implemented by stacking multiple dies which are vertically connected by TSVs. This enables that the global interconnects in the 3D chip can be shortened such that high performance improvement can be achieved. Furthermore, high bandwidth can be achieved due to the significant increase of IO interconnection density provided by the TSVs. In addition, the 3D integration technology provides many advantages over 2D integration technology, such as high functionality, low power, small form factor, and so on. However, many challenges on the design, electronic design automation (EDA), and testing should be overcome before volume production of 3D ICs using TSV becomes possible . Developing effective key techniques of design, EDA, and testing thus are imperative to cope with these challenges. Therefore, this proposal incorporates experts of mixed-signal design, EDA, and testing to attempt to develop some key techniques of design, EDA, and testing for 3D ICs. This three-year joint project entitled "Key Techniques of Design, Design Automation, and Testing for 3D ICs", is composed of four sub-projects which are listed as follows: Sub-project 1: Die-to-Die Interfacing Techniques for 3D ICs Sub-project 2: Heterogeneous System Exploration Platform and Power Planning Techniques for 3D ICs Sub-project 3: Performance-Driven Physical Design for 3D ICs Sub-project 4: Design-for-Testability Techniques and Automation for 3D ICs 研究期間：10008 ~ 10107 |
