應用於三維積體電路之設計、自動化與測試關鍵技術-子計畫三：應用於三維積體電路之效能導向實體設計自動化(I);Performance-Driven Physical Design for 3d Ics

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Title:	應用於三維積體電路之設計、自動化與測試關鍵技術-子計畫三：應用於三維積體電路之效能導向實體設計自動化(I);Performance-Driven Physical Design for 3d Ics
Authors:	陳泰蓁
Contributors:	電機工程學系
Keywords:	三維積體電路;擺置;繞線;矽穿孔;去耦電容;研究領域：電子電機工程類
Date:	2011-08-01
Issue Date:	2012-01-17 19:08:28 (UTC+8)
Publisher:	行政院國家科學委員會
Abstract:	對於處理大量記憶單元、運算單元及快速成長的電路連線，三維積體電路是目前最具有潛力的架構。三維積體電路的主要優點在於縮短與日俱增的電路互連長度。不僅如此，三維積體電路的其他優勢包括：(1)由於擁有較高的堆積密度，三維積體電路使晶片的體積更小；(2)由於縮短平均電路互連長度，三維積體電路擁有更高的性能表現；(3)由於縮減整體電路互連長度，三維積體電路減少功率的消耗；(4)三維積體電路可支援多重混合製程技術晶片的實現。相對於優勢，三維積體電路也帶來關鍵的挑戰，例如：效能、介面繞線、散熱、封裝和功率密度等問題。因此，在三維積體電路得以實現之前，發展相對應的電子設計自動化工具與設計流程，以克服此嚴峻的挑戰已勢在必行。這個三年計畫旨在提出數個有關三維積體電路的實體設計關鍵技術，以解決設計三維積體電路所帶來的挑戰。提出的實體設計關鍵技術包含三個重點項目：（1）三維積體電路繞線，（2）矽穿孔（TSV）規劃，以及（3）三維積體電路去耦電容（decoupling capacitance）設計自動化。對於三維積體電路繞線，需要考慮兩個相鄰晶粒間的繞線問題，也需要考量測試電路對正常電路繞線資源的影響。對於矽穿孔的規畫，需要考量溫度矽穿孔對溫度傳導的影響，訊號矽穿孔的位置對晶片效能的影響，以及訊號矽穿孔與高速傳輸電路或高速傳輸矽穿孔之間的影響。最後，對於三維積體電路去耦電容設計自動化，我們計畫利用三維積體電路不同於傳統二維積體電路的特性與元件，用來改善使用大量去耦電容而造成使用大量面積的缺點。Three-dimensional integrated circuits (3D ICs) are a promising alternative to handle the integration of large memories, functional units, and increasing interconnections in a chip. The key advantage of 3D ICs is the reduction on global interconnection length. Other advantages of 3D ICs include the following: (1) higher packing density and smaller footprint due to the addition of a third dimension to the conventional two-dimensional layout; (2) higher performance due to reduced average interconnection length; (3) lower interconnection power consumption due to the reduction in total wiring length; and (4) support for realization of mixed-technology chips. However, 3D ICs also incur several crucial challenges, e.g., performance problems, interface routing problems, thermal problems, packaging problems, power density problems, etc. Hence, to fully utilize the advantages of 3D ICs, it is desired to develop corresponding Electronic Design Automation (EDA) tools and design flows to overcome the addressed challenges. In this three-year project, we intend to propose several key techniques in EDA to tackle the design challenges induced by 3D ICs. Three major topics for proposed key techniques include: (1) routing for 3D ICs, (2) TSV planning, and (3) decoupling capacitance design automation for 3D ICs. For 3D IC routing, the interface router needs to consider the routing problem between two adjacent dies and the routing resource with test circuits. For TSV planning, we need to consider the performance of chips and high-speed circuits affected by the thermal and signal TSVs. For decoupling capacitance design automation, the distinctive characteristic and devices of 3D ICs are considered to improve the consuming usage of traditional decoupling capacitance. 研究期間：10008 ~ 10107
Relation:	財團法人國家實驗研究院科技政策研究與資訊中心
Appears in Collections:	[Department of Electrical Engineering] Research Project

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