A Low Loss High Isolation DC-60 GHz SPDT Traveling-Wave Switch With a Body Bias Technique in 90 nm CMOS Process

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Title:	A Low Loss High Isolation DC-60 GHz SPDT Traveling-Wave Switch With a Body Bias Technique in 90 nm CMOS Process
Authors:	Chang,HY;Chan,CY
Contributors:	電機工程學系
Date:	2010
Issue Date:	2012-03-28 10:09:57 (UTC+8)
Publisher:	國立中央大學
Abstract:	In this letter, a low loss high isolation broadband single-port double-throw (SPDT) traveling-wave switch using 90 nm CMOS technology is presented. A body bias technique is utilized to enhance the circuit performance of the switch, especially for the operation frequency above 30 GHz. The parasitic capacitance between the drain and source of the NMOS transistor can be further reduced using the negative body bias technique. Moreover, the insertion loss, the input 1 dB compression point (P(1) (dB)), and the third-order intermodulation (IMD3) of the switch are all improved. With the technique, the switch demonstrates an insertion loss of 3 dB and an isolation of better than 48 dB from dc to 60 GHz. The chip size of the proposed switch is 0.68 x 0.87 mm(2) with a core area of only 0.32 x 0.21 mm(2).
Relation:	IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS
Appears in Collections:	[Department of Electrical Engineering] journal & Dissertation

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