Testing Comparison and Delay Faults of TCAMs With Asymmetric Cells

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Title:	Testing Comparison and Delay Faults of TCAMs With Asymmetric Cells
Authors:	Li,JF
Contributors:	電機工程學系
Date:	2010
Issue Date:	2012-03-28 10:12:56 (UTC+8)
Publisher:	國立中央大學
Abstract:	Ternary content addressable memory (TCAM) is one key component in high-performance networking applications. An asymmetric TCAM cell consists of a binary content addressable memory (BCAM) bit and a mask bit. In this paper, we analyze comparison faults of the asymmetric TCAM cell based on BCAM comparison faults. Also, two delay faults for covering delay defects in the comparison circuits of a TCAM are proposed. Then two march-like test algorithms T(H) and T(PAE) are proposed to cover the comparison faults and delay faults of the comparison circuits in TCAMs with asymmetric cells. The test algorithm T(H) requires 7N Write operations and (3N + 2B) Compare operations to cover the comparison faults of an N x B-bit TCAM with Hit output only; and the test algorithm T(PAE) requires 4N Write operations and (3N + 2B) Compare operations to cover the comparison faults of an N x B-bit TCAM with priority address encoder (PAE) output.
Relation:	IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
Appears in Collections:	[Department of Electrical Engineering] journal & Dissertation

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