A 6-GHz Built-in Jitter Measurement Circuit Using Multiphase Sampler

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题名:	A 6-GHz Built-in Jitter Measurement Circuit Using Multiphase Sampler
作者:	Cheng,KH;Liu,JC;Huang,HY;Li,YL;Jhu,YJ
贡献者:	電機工程學系
日期:	2011
上传时间:	2012-03-28 10:13:19 (UTC+8)
出版者:	國立中央大學
摘要:	This brief presents a 6-GHz built-in jitter measurement (BIJM) with the time amplifier (TA) and the multiphase sampler (MPS) to achieve a 1-ps timing resolution. The proposed MPS can reduce the area, and the TA can extend the total timing resolution of BIJM. The self-referenced circuit with the autocalibration technique can eliminate the process variations and create a reference clock being a sampled signal. Using the calibration technique, the gain variation of TA and the timing resolution variation of MPS can be aligned to achieve a 1-ps timing resolution. The sense amplifier delay flip-flop uses the bulk input to reduce the measured error. The BIJM is fabricated by a 90-nm CMOS process. The core area of BIJM is 130 mu m x 200 mu m, and the power consumption is 20.4 mW with the I/O buffers.
關聯:	IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
显示于类别:	[電機工程學系] 期刊論文

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