Design Methodology for Yield Enhancement of Switched-Capacitor Analog Integrated Circuits

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題名:	Design Methodology for Yield Enhancement of Switched-Capacitor Analog Integrated Circuits
作者:	Luo,PW;Chen,JE;Wey,CL
貢獻者:	電機工程學系
關鍵詞:	PLACEMENT
日期:	2011
上傳時間:	2012-03-28 10:14:07 (UTC+8)
出版者:	國立中央大學
摘要:	Device mismatch plays an important role in the design of accurate analog circuits. The common centroid structure is commonly employed to reduce device mismatches caused by symmetrical layouts and processing gradients. Among the candidate placements generated by the common centroid approach, however, whichever achieves better matching is generally difficult to be determined without performing the time-consuming yield evaluation process. In addition, this rule-based methodology makes it difficult to achieve acceptable matching between multiple capacitors and to handle an irregular layout area. Based on a spatial correlation model, this study proposed a design methodology for yield enhancement of analog circuits using switched-capacitor techniques. An efficient and effective placement generator is developed to derive a placement for a circuit to achieve the highest or near highest correlation coefficient and thus accomplishing a better yield performance. A simple yield analysis is also developed to evaluate the achieved yield performance of a derived placement. Results show that the proposed methodology derives a placement which achieves better yield performance than those generated by the common centroid approach.
關聯:	IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES
顯示於類別:	[電機工程學系] 期刊論文

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