Design Planning with 3D-Via Optimization in Alternative Stacking Integrated Circuits

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Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/52053

Title:	Design Planning with 3D-Via Optimization in Alternative Stacking Integrated Circuits
Authors:	Lu,CH;Chen,HM;Liu,CNJ
Contributors:	電機工程學系
Keywords:	TO-WAFER STACKING;3D SYSTEM;TECHNOLOGY
Date:	2011
Issue Date:	2012-03-28 10:14:16 (UTC+8)
Publisher:	國立中央大學
Abstract:	Billions of transistors are placed in one single chip (SoC) with advanced manufacturing technology. Further development is obstructed by the ability to the manufacture of SoC and the signal integrity. Stacking IC is an alternative choice when we design a high-performance high-density chip. Design flow (especially physical design) is facing different issues when compared with 2D IC design. The location of the I/Os seriously affect the number of 3D-Vias and their total area in the stacking IC. This paper proposes a Stacking IC architecture and the corresponding design flow to solve the I/O and 3D-Via problems. In this flow, we have developed a system partition approach to minimize the number of 3D-Vias and balance the I/O number of each tier, and modified one traditional floorplan method to optimize the I/O and module locations. The experimental results are encouraging in the GSRC benchmarks. Compared with greedy and intuitive methods, our framework reduces the number of 3D-Vias by 30.02% on the average and can balance the I/O count of each tier. The dead space of the final floorplan is reduced by 14.13%.
Relation:	JOURNAL OF INFORMATION SCIENCE AND ENGINEERING
Appears in Collections:	[Department of Electrical Engineering] journal & Dissertation

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