混合訊號電路可製造性設計技術;Development of Design-for-Manufacturability Techniques for Mixed-Signal IPs

NCUIR > College of Electrical Engineering & Computer Science > Department of Electrical Engineering > Research Project > Item 987654321/57378

Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/57378

Title:	混合訊號電路可製造性設計技術;Development of Design-for-Manufacturability Techniques for Mixed-Signal IPs
Authors:	陳竹一
Contributors:	中央大學電機工程學系
Keywords:	電子電機工程類;自動佈局﹐良率預估﹐製程變動﹐良率分析﹐蒙地卡羅方法﹐最差狀況電路分析﹐名目值設計﹐容忍設計;Automatic Layout;Yield Prediction;Process Variation;Yield Analysis;MonteCarlo Method;Worst Case Circuit Analysis;Nominal Design;Tolerance Design
Date:	2008-09-01
Issue Date:	2012-10-01 15:19:34 (UTC+8)
Publisher:	行政院國家科學委員會
Abstract:	本計畫“混合訊號電路可製造性設計技術”為“用於混合訊號與記憶體矽智產之DFX 技術”的一子計畫。在本計畫中，研究包括三項主題：(1) 最差狀況電路分析與容忍設計， (2)類比電路自動佈局擺置和(3) 類比電路自動佈局繞線。計畫目的希望能開發一考量變動，使用相依變動警覺模擬的自動佈局平台，以適應奈米時代單晶片系統量產可行性設計。最差狀況電路分析，模擬時考量製程、元件、電路結構和操作環境等變動因素，以蒙地卡羅法，對電路性能做最差狀況預估；容忍設計在於引入良率相當的模型參數，以探索空間相關性對積體電路性能的影響，亦即，研究在先進製程中製程變動的效應，以增進設計良率。同時，有別於對稱匹配的法則，利用同質且等向隨機的空間相關性，能為實體層設計時，提出一新穎的元件擺置方法，開發類比電路自動佈局擺置和繞線平台，以達到混合訊號積體電路設計快速、高精確度、高良率、高品質的需求。吾人欲以 Matlab 為發展平台，整合各個目前設計流程中的模擬設計工具，例如線路模擬器Hspice，佈局軟體Laker 等。以常見的運算放大器、數位類比轉換器及和差調解器為實例，實際測試所開發的分析設計平台。 ; This project “Development of Design-for-manufacturability Techniques for Mixed-Signal IPs” is a sub-project of “Development of Design-for-X-ability (DFX) techniques for Mixed-Signal and Memory IPs.” In this sub-project, it is to study three topics, i.e., (1) Worst Case Circuit Analysis and Tolerance Design, (2) Automatic Analog Layout Placement, and (3) Automatic Analog Layout Routing, with the aims to develop an automatic layout platform through the use of DfD (design for dependentability) and variation-aware simulators, in order to accommodate with the need of design for manufacturability in a nanometer technology era. In the sub-topic of worst case circuit analysis, it is to estimate the extreme case of the circuit performances by introducing the yield-related metrics through the use of a Monte Carlo simulator. Multiple aspects such as manufacturability and reliability are to be explored by consideration of various parametric domains including manufacturing process, devices, circuit structures, and operational environment due to larger amount of process variations (PVT variations). During the phase of tolerance design, it is to explore how the circuit performance is affected by the spatial correlation in advanced technology and to improve the design yield. It is, in turn, to propose a novel design methodology for device allocation in physical design stage, including layout placement and routing, by using the capability of homogeneous isotropic random (HIR) spatial correlation for high-speed, high-precision, high yield and high quality of mixed-signal IC design. Our system platform will be developed in Matlab by integrated with the simulation and design tools, like Hspice and Laker, in current design flow. The common circuits of Op-Amp, Degital to Analog Converter (DAC), and sigma-delta modulator are used to verify the developed platform. ; 研究期間 9708 ~ 9807
Relation:	財團法人國家實驗研究院科技政策研究與資訊中心
Appears in Collections:	[Department of Electrical Engineering] Research Project

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