三微晶片(3D IC)的矽穿孔(TSV)為了達到高密度，高頻寬以及高速傳輸， 而被廣泛使用因此導致矽穿孔密度增加。但是兩訊號互相干擾將會造成訊號的傳輸品質發生問題，即是我們所提到的耦合雜訊。 本論文主要討論矽穿孔的耦合效應，其主要來源是由矽穿孔與矽基板之間的絕緣層產生的電容，雜訊再由電容向矽基板發散。最大的兩個耦合雜訊為矽穿孔對矽穿孔的耦合雜訊以及矽穿孔對電路的耦合雜訊。接著提出等效垂直十字鏈基板結構 (Vertical-Cross-Chain Substrate Structure ; VCCSS) ，利用此結構來模擬矽穿孔 (TSV) 之間的耦合雜訊效應並加強大約為11.5%的精準度。 我們還設計出一個矽穿孔的分析平台，能夠將設計完的電路整合到Hspice，讓我們可以快速產生電路架構並且進行模擬分析，其中我們還可以使用兩種不同的基板(EPI基板跟High-R基板)來進行分析模擬。若如果要以能量觀點來分析矽穿孔的話，我們未來也能將此分析平台整合到ADS模擬軟體裡，能夠減少電路架構的時間。甚者，我們未來也可以使用平台來達成晶片堆疊，進而去更細膩的分析電路完整結構。接著使用各種不同的屏蔽技巧 (Shielding Technique) ，並且在矽穿孔的Aggressor-Victim Pair陣列中利用改變製程參數，保護環 (Guard-Ring) 與矽穿孔 (TSV) 的間距以及不同擺放來觀察矽穿孔(TSV) 的底部到頂部會有一個縱向延伸效應(Vertical Extension Effect) 的變化以及抑制。In order to achieve high density, high bandwidth and high transmission, Through-Silicon-Via(TSV) has been widely used in three-dimensional chip integration thus resulting its density is increased. However the quality of signal transmission may be a tremendous problem on the ends of two signals interfering with each other. That is, we mentioned “coupling”. This thesis is focused on the TSV coupling effect. Its main source is generated by the insulator capacitance between TSV and silicon substrate, and then coupling noise disperse from insulator to capacitance. The two most important coupling noises are “TSV-to-TSV coupling noise” and “TSV-to-circuit coupling noise”. And a signal transmission analysis platform for an advanced TSV model, called Vertical-Cross-Chain Substrate Structure (VCCSS), is performed to simulate and discuss with the TSV coupling effect, where the enhancement of the simulation accuracy is up to 11.5%. The TSV analysis platform, which can generate circuit architecture quickly and execute simulation analysis, is with the core by integrating the circuit simulation to Hspice or ADS. It is also to be extended to simulate the circuit with two kinds of substrate (EPI substrate & High-R substrate). If the analysis of the energy point of TSV is desired, this platform may automatically integrate the circuit simulation to ADS in order to reduce the time of setting up the circuit structure. Furthermore, we can achieve chip-stacking by using this analysis platform and then to analyze the whole circuit structure more carefully. Then we use a variety of shielding techniques, by changing the parameters of the process, the spacing between guard ring and TSV and different placement of guard ring in aggressor-victim pair array, we can observe the changes and suppression of vertical extension effect from bottom to top of TSV.
