現今的製程已經達到奈米層級，在元件(device)上因製造(manufacture)時所產生的變異(variation)隨處可見，而且變異所造成的影響將隨著元件縮小而呈現指數成長，在未來的製程中它將成為一個嚴重的問題。當製程變異造成電路效能變化過大時，可能會造成電路設計失效(design failed)，而導致晶片製造良率(yield)下降，傳統上，在晶片正式下線之前需要進行角落分析(Corner Analysis)，以保證出貨的晶片有著一定的良率，這也是晶圓廠對客戶的最低要求。 角落分析最重要的功能就是預估電路的最差情形，讓使用者去改善電路而讓良率增加。以往進行角落分析時，只考慮製程變異(process variation)的5種角落，這很容易可以進行徹底的角落分析；而在現今製程中，需要把電源(voltage)及溫度(temperature)的變異也考慮進去，因此，一個設計要徹底地進行角落分析，可能有數百或數千個角落需要進行模擬，這是非常耗時的。本論文提出一個演算法有效地萃取出合適的角落(corners)，讓設計者不需要對所有角落進行模擬，只需要少量的模擬，就能找出最差的情形，大大的改善了良率分析的效率。 In today’s nanometer IC process, process variation in devices is a common phenomenon. This process variation problem gets exponentially worse as device size shrinks, which will become a big issue in the future. If process variation changes the chip performance too much, it could make the design fail to meet the specification and reduce the design yield. Before tape-out, foundry will ask the customer to do corner analysis as least to guarantee the design yield. The goal of corner analysis is to find the worst-case performance values across all PVT corners. If the yield is not good, the designers can redesign the circuits before tape out. Traditionally, there are only 5 process corners. It’s quite easy to run full corner analysis. In modern designs, the variations of supply voltage and temperature should be considered, too. Therefore, there can be hundreds or thousands of PVT corners. This is quite time-consuming to run full corner analysis. This thesis proposes an algorithm to extract the most relevant corners to be simulated. Instead of full corner analysis, only a few simulations are enough to find the worst case among all corners. As shown in the experimental results, this approach greatly improves the efficiency and accuracy of design yield analysis.
