應用積體電路上方後製程與整合被動元件於互補式金氧半導體製程之系統封裝研究; Study of System-in-Package Technology using Above-IC Post Process and Integrated Passive Device on CMOS Process

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题名:	應用積體電路上方後製程與整合被動元件於互補式金氧半導體製程之系統封裝研究;Study of System-in-Package Technology using Above-IC Post Process and Integrated Passive Device on CMOS Process
作者:	許源佳;Hsu,Yuan-Chia
贡献者:	電機工程學系
关键词:	系統封裝;積體電路上方後製程;整合被動元件;互補式金氧半導體;帶通濾波器;壓控震盪器;system-in-package;above-IC post process;integrated passive device;CMOS;band-pass filter;voltage controlled oscillators
日期:	2013-08-14
上传时间:	2013-10-08 15:24:00 (UTC+8)
出版者:	國立中央大學
摘要:	本篇論文主要研究系統封裝設計的實現方法，利用積體電路上方後製程與整合被動元件兩種製程技術，完成“操作在60 GHz的帶通濾波器”及“互補式金氧半導體與積體電路上方後製程”和“互補式金氧半導體與整合被動元件”之壓控震盪器兩類電路。整合被動元件為低損耗的薄膜製程，利用此製程的高性能優勢，實現一個操作在60 GHz之帶通濾波器，最小介入損耗為1.72 dB (當頻率為57 GHz)，在57- 64 GHz的7 GHz頻寬中，介入損耗都小於2.4 dB，且3-dB頻寬有24 GHz (~42%)。第一個壓控振盪器是利用覆晶技術組裝操作在5 GHz互補式金氧半導體與整合被動元件之壓控震盪器，並提出完整“互補式金氧半導體與整合被動元件”協同模擬的設計流程，探討不同整合被動元件-電感擺放的位置(遠離或接近主動元件)對電路特性的影響，實驗結果顯示不論是遠離或接近主動元件相位雜訊都可以達到-120 dBc/Hz(偏移頻率在1 MHz位置)，相較於全積體化的金氧半導體壓控震盪器，本論文電路改善了6.7 dBc/Hz的相位雜訊。第二種電路為互補式金氧半導體與積體電路上方後製程之壓控震盪器，操作頻帶在5 GHz，利用高品質因素的積體電路上方電感，使壓控震盪器得到較低相位雜訊，相較於全積體化的金氧半導體製程之壓控震盪器，相位雜訊可改善6.4 dBc/Hz (偏移頻率在1 MHz位置)。此外論文中也探討積體電路上方後製程電感接地的方式對電路之影響，實驗結果顯示接地要遠離矽基板才可獲得高品質的特性。 This dissertation studies the design approaches of system-in-package. Using above-IC post process and integrated passive device (IPD) techniques, we realize a band-pass filter operating at 60GHz and two voltage controlled oscillators (VCOs). One is a CMOS VCO mounted on integrated passive device chip, namely CMOS-IPD VCO, the other is CMOS chip with inductor fabricated by above-IC post process technique, namely CMOS VCO with above-IC inductor. Using the advantage of IPD process, a band-pass filter is implemented and operating over the unlicensed 60-GHz band (57-64 GHz). The experimental results show the minimum insertion loss is 1.72 dB at 57 GHz, the insertion loss is 2.4 dB over the entire 7 GHz pass band, and its 3-dB bandwidth is 24 GHz (~42%). The first CMOS VCO with IPD chip is assembled by flip-chip technology. The design flow of CMOS chip with IPD technology is also proposed to investigate the effects of IPD inductors placed at different location on the top of the CMOS chips. The experimental results show that the VCO can achieve a phase noise of -120 dBc/Hz at 1-MHz offset frequency no matter what place the inductor is located. An improvement of 6.7dB is demonstrated in comparison with a fully integrated CMOS VCO. The second 5GHz CMOS VCO designed and implemented with above-IC inductor demonstrates a measured phase noise of -120 dBc/Hz at 1-MHz offset frequency, 6.4-dB improvement in comparison with a fully integrated CMOS VCO. The grounding issue of inductor on the CMOS and above-IC post process was also carefully examined by the electromagnetic (EM) simulation in this dissertation.
显示于类别:	[電機工程研究所] 博碩士論文

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