高速 850-nm 矽光檢測器設計與分析; Design and Analysis of 850 nm Si Photodiodes in Standard CMOS Technology

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Title:	高速 850-nm 矽光檢測器設計與分析;Design and Analysis of 850 nm Si Photodiodes in Standard CMOS Technology
Authors:	周芳嬪;Chou,Fang-ping
Contributors:	電機工程學系
Keywords:	光檢測器;標準製程;Photodiodes;CMOS;850 nm
Date:	2013-08-26
Issue Date:	2013-10-08 15:24:52 (UTC+8)
Publisher:	國立中央大學
Abstract:	本論文所討論的光通訊元件為利用較便宜的矽（Silicon）材料並結合商用標準 CMOS 製程製作的矽光檢測器(Si photodetector)，利用此方式製作的元件俱有大幅降低成本及容易與後端電路整合製成光電積體電路（OEIC）的特性。使用商用 CMOS 製程來實現 850-nm 光檢測器最關鍵的問題其一便是速度，由於商用 CMOS 製程屬於平坦化且表面的製程，實際可應用的 n/p 層(layer)最深也只在 2 ~ 3 ?m 之間。對入射光波長為 850 nm 的光訊號而言，矽材料的吸收深度(absorption depth)約為 20-?m，此意味著大部分的光會落在表面元件之外的基板中，無法直接被表層形成的元件空乏區內之電場收集到。這些在基板中吸光而產生的電子電洞對，會先以擴散運動方式慢速的到達空乏區而被電極收集，因而大幅地影響了光檢測器的操作速度。加上標準 CMOS 製程無法更動製程條件，元件的設計與特性改善只能利用現有層數和佈局來改善。研究上首先利用基本 pn 二極體結構的光檢測器(PD)來比較三種不同形狀佈局光檢測器的表現，包括傳統長條型、環繞式四邊形、與環繞式八邊型，量測結果顯示，環繞式八邊型的結構有對稱電場分佈能達到較佳的頻寬、響應度表現，因此本論文的後續正面照光光檢測器都採用八邊型的佈局。為了改善光檢測器的速度特性，提出了三種方法來達到高速的目標。第一種方法是利用 pwell 包圍在元件最外圍形成一圈 body 的結構，接下來給予 body 電極適當的偏壓，讓其與光檢測器內部接地的 p 端形成電流路徑。當基板因照光產生慢速載子而往元件主動區移動時，慢速載子會被此電流路徑帶走而不影響元件本身，進而提高元件的頻寬。並且透過適當的 body 偏壓與 PD 元件偏壓配合，能讓元件操作在低偏壓 3-V 達到頻寬 2.46GHz，符合實際的低壓操作運用。第二個方法是利用側面照光的方式，將光藉由側面照射至元件表面，避免入射光照射到基板，減少基板產生慢速載子的困擾。但標準製程實現測照 PD 的困難在於如何定義受光面，本論文利用 CIC 提供的後製程(MEMS)蝕刻出受光面，再用切割的方式露出受光面以利光纖照光。基本 pn 結構為長條型，光檢測器頻寬由正面入射照的 1.4 GHz 提升至側面入射照的 2.6GHz。第三種方法是利用 0.18 ?m CMOS 製程裡的較深層 deep n-well 來阻擋基板的慢速載子，若要確實達到阻隔慢速載子必須要在 deep n-well 增加額外的電極來將電子帶走加上，並利用基板接地帶走慢速電洞共同達成。此方法的光檢測器頻寬可大幅提升至 8.7 GHz，為目前文獻上利用商用 CMOS 製程實現的最快速 850-nm 矽光檢測器。除了利用頻寬來確認基板慢速載子的排除效果，另外也藉由多餘噪音雜訊(excess noise) 的量測結果來佐證，比較三種研究方法的元件之多餘噪音雜訊量測結果，矽光檢測器具有 deep n-well 另給偏壓的方式可以得到最低雜訊指數(noise factor) 5.3。 This dissertation proposes the photodetectors using cheaper silicon material combined with standard CMOS technology without any process modifications. To enable the cost-effective implementation of the optical short-distance interconnection, Si CMOS technologies is a good, low-cost approach for general 850 nm transmitter and provide a universal platform for the monolithic integration of available, complex, and high-speed circuits with Si photodetectors to form an all-Si optical receiver (OEIC). One of the most crucial issues for 850 nm Si photodiodes in standard CMOS technology is the response speed. Because the penetration depth (? 20 μm) of the 850 nm-wavelength light into Si is much deeper than that of the depth of the depletion (? 2 μm) in the surface p-n diodes. As a result, a large portion of carriers is generated in the Si substrate and diffuse in all directions. The slow diffusion carriers will reach the depletion region and led to the slow response of the p-n PD. Researchers have studied several device layouts to optimize device performance. Silicon photodiodes (PDs) with different layouts in standard 0.18-μm CMOS technology are systematically presented and discussed first in this dissertation. Different layout geometries of PDs are realized including conventional rectangle, square and octagon layouts. A basic p-n PD with octagon layout demonstrates higher responsivity and lower capacitance with improved bandwidth. Therefore, the vertically illuminated PDs with octagonal layout are used in this dissertation. To improve the speed characteristics of the photodetector, three methods are proposed to improve the bandwidth. First, a basic p-n PD with body contact presents a method to eliminate the slow photocarriers by adopting a body contact design to create a current ?ow under the PD to remove the slow diffusion carriers.. With the appropriate bias between PD and body contact, a low bias and high-speed PD can be achieved for practical applications. The 3dB bandwidth of PD is 2.46 GHz at low bias 3 V. Secondly, the edge-illuminated Si PDs with standard CMOS technology by employing an MEMS process to expose the coupling edge surface is realized. A single-mode lensed fiber is employed to inject light into the depletion region of the PD, thereby limiting and reducing the diffusive carriers within the bulk Si substrate. Consequently, the edge-illuminated PD with conventional rectangle layout shows the improved 3-dB bandwidth from 1.4 GHz to 2.6 GHz in comparison to the vertically illuminated Si PDs. The third method is that using deep n-well implantation in standard CMOS technology to block the slow diffusion carriers from substrate. Two different bias schemes (normal bias and extra bias) on the deep n-well are used to analyze the effects of deep n-well bias on the bandwidth and gain-bandwidth performances of Si PDs. The extra bias in the PD not only blocks the hole and collects electrons from the substrate, but also improves the PD performance. This design achieves the highest bandwidth (8.7 GHz) and a large gain-bandwidth product of 542 GHz with a reverse bias of 11.45 V and an extra voltage of 11.45 V but low-magnitude of output signal in standard CMOS technology. This is the highest bandwidth reported for silicon photodetectors fabricated using standard CMOS technology and the highest gain-bandwidth product in 0.18 ?m CMOS technology. In addition to bandwidth, excess noise measurement is a way to confirm the effect of excluding substrate carrier. Si PDs in this dissertation with extra bias in the deep n-well demonstrates the lowest noise figure (noise factor) of 5.3 due to the removal of slow diffusion carriers.
Appears in Collections:	[Graduate Institute of Electrical Engineering] Electronic Thesis & Dissertation

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