| 摘要: | 射頻收發機中，壓控振盪器為一不可或缺的電路區塊，其功能在於提供系統穩定的訊號源，以對發射和接收信號進行升頻與降頻。壓控振盪器的重要性能參數包括頻率調整幅度、相位雜訊、直流功率消耗及射頻輸出功率等。
隨著電子科技的飛躍使數位化生活得以實現，在數位化家居生活的情境中，影音資料等多媒體內容傳輸是不可或缺的應用。近年來高畫質視訊傳輸的需求亦隨之興起，用於高畫質視訊無線傳輸的通訊標準也相繼制定，其中包括使用60 GHz頻段的WirelessHD及使用5 GHz ISM頻段的WHDI。在一般無線收發前端中，通常會使用兩個相位相差90°的射頻訊號來對基頻I與Q訊號進行調變及解調變；因此本論文首先探討一個60 GHz正交壓控振盪器，可產生無線前端所需之正交射頻訊號。本電路使用TSMC 90-nm CMOS製程實現，並採用傳統並聯式正交壓控振盪器的架構。當控制電壓由0 V調至1.2 V，振盪頻率可由60.61 GHz調至63.01 GHz，頻率調整幅度約為3.88%。於10-MHz offset之最佳相位雜訊與FoM分別為?89.61 dBc/Hz與?155.1 dBc/Hz。在頻率可調範圍內，輸出功率為?25.8±2 dBm，核心直流功耗小於11.1 mW；控制電壓為0.4 V時，最小相位及振幅誤差分別為3.25°/0.39 dB。
其次，在射頻前端子系統中，測試為數眾多的電路區塊是一件相當花費成本及時間的工作。如果各電路區塊本身具有即時監控及自我檢測的功能，可以大幅降低電路測試的時間及成本。於是我們將波包偵測器整合至一壓控振盪器內，藉著找出射頻輸出功率與偵測器輸出電壓之關係，來驗證此概念。操作頻段與使用製程分別為X頻段與TSMC 0.18-μm CMOS。電路使用LC-tank交錯耦合式振盪器架構；在1.8 V供應電壓下，當控制電壓由0 V調至1.8 V，振盪頻率可從9.25 GHz調至12.08 GHz，頻率調整幅度約為26.6%；此電路的最佳相位雜訊與FoM在1-MHz offset分別為?116.3 dBc/Hz與?182.7 dBc/Hz；在頻率可調範圍內，輸出功率為8±0.4 dBm，核心直流功耗小於17.37 mW；波包偵測器之輸出電壓約為60±20 mV。
我們成功地設計及實現一個可應用於數位家庭之60 GHz正交壓控振盪器；此外，我們整合一波包偵測器於壓控振盪器中，驗證其射頻輸出功率與偵測電壓之間的對應關係，期能應用於射頻內建自我測試。
In RF transceivers, voltage controlled oscillator (VCO) is an indispensable circuit block. The function of a VCO is to provide a stable signal source for up-converting and down-converting the transmitted and received signals, respectively. Important metrics for VCO include frequency tuning range, phase noise, DC power consumption, and RF output power.
The advance of electronic technology enables digital life. In digital-home scenario, the transmission of multimedia content with both video and audio is necessary. In recent years, the demand for high-definition (HD) video transmission has increased and the associated wireless standards are successively defined, including WirelessHD and WHDI, which use 60-GHz band and 5-GHz ISM band, respectively. For wireless transceivers, it is a common practice to use two RF signals whose phases are 90° in difference to modulate or demondulate the baseband I/Q signals. Therefore, we first develop a 60-GHz quadrature VCO (QVCO), which can provide the quadrature RF signals required in wireless front-ends. The circuit adopts traditional parallel-QVCO topology and is implemented using TSMC 90-nm CMOS techonology. The measured oscillation frequency can be tuned from 60.61 GHz to 63.01 GHz, which corresponds a frequency tuning range of 3.88%, as the control voltage is swept from 0 V to 1.2 V. At 10-MHz offset, the minimum phase noise and FoM are ?89.61 dBc/Hz and ?155.1 dBc/Hz, respectively. With the frequency tuning range, the output power is ?25.8±2 dBm and DC power consumption of the VCO core is less than 11.1 mW. At control voltage is 0.4 V, the minimum phase and amplitude error are 3.25° and 0.39 dB, respectively.
Next, in an RF system with numerous circuit blocks, the testing could be costly and time-consuming. To overcome this difficulty, the concept of built-in self test (BIST) can be applied. BIST would not only reduce the cost of testing but provide the capability of real-time monitoring. We design a VCO that has built-in envelope detectors integrated with it and demonstrate its potential for RF BIST by relating the output voltage of the detectors with the output power of the VCO. The VCO is designed and implemented in TSMC 0.18-μm CMOS. On 1.8-V supply, the measured oscillation frequency is from 9.25 GHz to 12.08 GHz, translating into a tuning range of 26.6%, as the control voltage is swept from 0 V to 1.8 V. At 1-MHz offset, the minimum phase noise and FoM are ?116.3 dBc/Hz and ?182.7 dBc/Hz, respectively. With the frequency tuning range, the output power is 8±0.4 dBm, the DC power consumption of the VCO core is less than 17.37 mW, and the detected output voltage is 60±20 mV.
In this work, a 60-GHz QVCO for digital home application is designed and measured. In addition, a VCO with built-in envelop detector is designed and measured. The relation between its detector output voltage and output power is found, demonstrating its potential for RF BIST. |
