摘要 本論文提出一個操作在6 GHz、擁有10個相位輸出全數位式展頻時脈產生器。在此設計中，本設計使用含有次回授迴圈之多重相位數位控制震盪器，因此可在相位多的情況下仍能有高頻率輸出。提出一個高速相位選擇器可以在6 GHz操作速度下做多相位的切換，相位選擇器中的相位選擇單元可以限制各節點所看到的負載，因此操作速度不受相位個數所影響。使用混亂波做為展頻機制的調變波型，藉以達到比其他種調變波型更多的電磁雜訊干擾衰減量。 本論文之全數位式展頻時脈產生器使用TSMC 90 nm MSG 1P9M CMOS製程實現晶片，其操作頻率為6 GHz，並且擁有10個相位的輸出。電路在操作電壓為1 V時，功率消耗為46 mW，而使用三角波調變的展頻機制對於電磁雜訊的衰減量為15.83 dB，使用混亂波調變的展頻機制對於電磁雜訊的衰減量為18.64 dB。整體晶片面積為830 × 830 um2，核心電路的面積為130 × 234 um2。 Abstract A 6 GHz all-digital spread-spectrum clock generator with 10-phase output has been presented in this thesis. A multi-phase digitally-controlled oscillator with sub-feedback loop has been used in this design, as a result, this circuit can be operating at high frequency with many outputs. The proposed high speed phase selector can switch phase at 6 GHz operating frequency. The phase-selecting unit in the phase selector makes load of each nodes limited, therefore, the operating frequency isn't affected by the amount of phase. The chaotic modu- lation used in the spread-spectrum mechanism increases the more reduction of electromagne- tic interference with comparison to other modulations. The proposed all-digital spread-spectrum clock generator has been fabricated in TSMC 90 nm MSG 1P9M CMOS process with 10-phase output at 6 GHz operating frequency. The power consumption is 46 mW under 1 V supply voltage. The reduction of electromagnetic interference are 15.83 dB with the spread-spectrum mechanism modulated by triangular wave and 18.64 dB with the spread-spectrum mechanism modulated by chaotic wave. The chip area is 830 × 830 um2. The core area is 130 × 234 um2.
