本論文實現了一個快速鎖定的鎖相迴路，在不使用電感的狀況下，使用四級雙端延 遲元件組成之震盪器能提供八個相位震盪頻率為5 GHz的輸出訊號。整體電路架構採用了多頻帶的電壓控制震盪器來降低KVCO，並利用頻帶選擇器決定出合適的頻帶。為了加速頻帶上的追鎖過程則使用了可適性相位頻率偵測器，使控制電壓能較為迅捷地改變，藉此快速消弭相位差，達到快速鎖定的效果。 本論文實現之具數位頻帶選擇器和可適性相位頻率偵測器之快速鎖定鎖相迴路使 用TSMC 90 nm(TN90GUTM) 1P9M 製程來實現，電路操作電壓為1 V。鎖相迴路的輸入參考時脈為50 MHz，輸出頻率鎖定在5 GHz，鎖定時輸出時脈抖動量為10.3 ps(pk-pk)。鎖定時間為1.6 us，功率消耗為10.1 mW，晶片面積為924.58 924.58 um2，核心電路部分面積則為236.23313.54 um2。 In this thesis, a fast locking PLL is proposed. Its oscillator is composed of 4-stage differential delay cells and can output 8 phase, 5 GHz clock signals without using inductors.The oscillator adopts multi-band architecture to lower the gain of the voltage controlled oscillator, KVCO, and the band selector picks out the adequate band to lock in. The adaptive phase frequency detector speed up the intra-band tracking so that the control voltage(VC)could vary agilely and the phase difference could be eliminated rapidly. This study was implemented by TSMC 90 nm(TN90GUTM) 1P9M process with 1 V supply voltage. A 50 MHz clock is used to be input reference clock of PLL, and the output frequency is 5 GHz. The period jitter of output frequency is 10.3 ps(pk-pk). The locking time of the proposed PLL is 1.6 us at 5 GHz and the power consumption of the PLL is 10.1 mW. The chip area is 924.58 924.58 um2 and the core area is 236.23 x 313.54 um2.
