時脈電路的新關鍵技術及應用;The Newly Key Techniques and Applications for Clock Circuit

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Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/62082

Title:	時脈電路的新關鍵技術及應用;The Newly Key Techniques and Applications for Clock Circuit
Authors:	鄭國興
Contributors:	國立中央大學電機工程學系
Keywords:	電子電機工程
Date:	2014-03-11
Issue Date:	2014-03-11 15:11:23 (UTC+8)
Publisher:	行政院國家科學委員會
Abstract:	研究期間：10308~10407;As the concept of the phase-locked loop (PLL) is presented in 1930, it has been widely used for the electronic and communicated product. The critical technique, namely, the PLL circuit, is commonly applied to the applications of clock synchronization. However, the trend of the general design consideration, meaning the low jitter, high operating frequency, fast locking for the clock circuits, has been toward the specific and replaceable applications. As a result, we would implement the clock circuits fabricated in 90/40 nm CMOS process for the different functions in this three-year proposal. In addition to the considerations of process, voltage, and temperature variations (PVT), we would also develop the relative technique for the low voltage and supply noise suppression. In the first year, we would focus on the design of the all-digital fractional-N frequency synthesizer, which is based on the PLL technique for the low jitter and clock synchronization. Thus, such design could release the features of high reliability, low area, low cost, and analog-less noise interference. Besides, for the double data rate synchronous dynamic random access memory interface (DDR) system, we would use the pulse width control loop (PWCL) to accurately control the duty cycle of the clock signal. In the second year, we would implement the all-digital spread spectrum clock generator (All-digital) SSCG for the electromagnetic interference (EMI) reduction in high-speed data transmission systems. In terms of the memory clock design, we would use digital de-skewing technique to synchronize the internal clock of the memory. In addition, the supply noise suppression and low voltage technique would also be proposed to support the other building block of the clock circuits. Finally, in the third year, we would develop the design of the low area and low power crystal-less oscillator, and integrate PWCL and the digital de-skewing technique with the DDR system. Moreover, we also utilize the PLL into the DC-DC converter to replace the traditional method, which indicates that the PLL controls the delay time to determine the switching frequency.
Relation:	財團法人國家實驗研究院科技政策研究與資訊中心
Appears in Collections:	[Department of Electrical Engineering] Research Project

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