應用於智慧生活與照護之節能感測網路---子計畫五：應用於無線感測網路之積體電路設計與佈局自動化技術( I );Design Automation for Wireless Sensor Network (I)

NCUIR > College of Electrical Engineering & Computer Science > Department of Electrical Engineering > Research Project > Item 987654321/63173

Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/63173

Title:	應用於智慧生活與照護之節能感測網路---子計畫五：應用於無線感測網路之積體電路設計與佈局自動化技術( I );Design Automation for Wireless Sensor Network (I)
Authors:	陳泰蓁;劉建男
Contributors:	國立中央大學電機工程學系
Keywords:	電子電機工程;護理學
Date:	2013-12-01
Issue Date:	2014-03-17 14:20:50 (UTC+8)
Publisher:	行政院國家科學委員會
Abstract:	研究期間：10205~10304;In wireless sensor networks, a smart sensor node (SSN) is required to have the self-power, the sensing signal, the transmission signal, the computing functions, and so on. Therefore, an SSN contains digital and analog units. PCB with high-speed transmission or SoC technologies are often be used to integrate an SSN. To maintain the signal integrity in PCB technology, finding suitable routing paths for high-speed transmission lines and general signals is a challenging issue. SoC technology increases the circuit complexity and results in hard precisely to detect design errors in circuit validation. Physical probing technologies can be used to overcome the difficulty and focused ion beam (FIB) is the most popular one. Making a layout that is suitable to apply FIB in SoC is another challenging issue since the increasing circuit complexity decreases the successful rate of FIB. Due to the layout parasitic effects have a high influence on the performance sensitivity of analog circuits, considering complex characteristic of the devices and interconnects are needed for high-performance analog layout. It is hard to evaluate the circuit performance before the layout generated since the estimated ideal characteristic will be degraded due to the layout parasitic effects. Since layout is a key step to make an analog circuit work, we need to have a smart methodology to estimate the layout parasitic effects before the layout generated and a smart simultaneous placement and routing technique. The subproject has two major missions. The first mission is to prove effectively optimizing techniques for the key issues of mixed-signal integration flow. The optimizing techniques can make the design flow more smooth and speed-up the development schedule. Another mission is to develop an advanced and practical design automation platform for analog circuits. The platform considers the layout parasitic effects during the sizing and place & route stages to make the platform can be applied in real circuits. We hope this work can fully assist designers and make the time-to-market shorten by automate sizing, placement, and routing.
Relation:	財團法人國家實驗研究院科技政策研究與資訊中心
Appears in Collections:	[Department of Electrical Engineering] Research Project

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