及時驗證於基頻發射機是經由此發射機發射一DVB-T訊號載上一較低的中頻載波後，經由電力線通道來實現與展示。及時發射機包含了FPGA以及數位類比轉換器及電力線通訊類比前級電路 。發射的DVB-T訊號經由另一個電力線通訊接收模塊收回後，以離線後以接收機的演算法來分析接收到的訊號。;Digital Video Broadcasting–Terrestrial (DVB-T) is the digital television broadcasting standard specified by the European Broadcasting Union, which is also adopted in Taiwan.
In this thesis, we design and realize a real-time hardware baseband transmitter for DVB-T using FPGA. The architecture of the transmitter is comprised of the following main modules: Reed-Solomon code encoder, outer interleaver, convolutional code encoder with puncher, innner interleaver (bit, symbol), IFFT processor, Cyclic-Prefix generator and digital-upconverter. The design issues include interfacing/synchronization between multi-rate modules, fixed-point resolution of the IFFT processor and the lowpass filter in the digital-upconverter. In the design phase, we first use MATLAB for modeling and analysis to obtain an appropriate design which tradeoffs the system performance/accuracy with estimated hardware complexity. In the implementation phase, Verilog hardware description language is used for coding the hardware system followed by logic behavior and real-time verifications with ModelSim and FPGA platform, respectively.
The real-time verification of the baseband transmitter is achieved by a realization and demonstration of a real-time transmitter which transmits the DVB-T signal with a lower IF carrier through the power-line channel. The real-time transmitter comprises of the FPGA platform which is loaded with the transmitter design, the Digital-to-Ananlog module and the power-line communication (PLC) analog frontend. The transmitted DVB-T signal is captured by another PLC receiver platform and then is analyzed by off-line receiver algorithm which verifies the real-time transmitted signal.
