| 摘要: | 本文利用tsmcTM提供的0.18-um CMOS 與90-nm CMOS製程實現操作於微波K頻段之低功耗壓控振盪器。本論文將介紹與探討壓控振盪器之雜訊生成機制，並應用多樣的磁耦合變壓器設計於低功耗之操作，以改善相位雜訊，並且以實作的量測結果驗證電路理論設計之正確性。
其設計內容包括三個壓控振盪器如下：
一、設計一應用耦合變壓器技術之低功耗互補式壓控振盪器，使用閘極電感增加迴路增益，使振盪條件更容易達成，使用tsmcTM 0.18-μm CMOS製程，其振盪頻率為23.46 GHz，可調頻率範圍600 MHz，偏移主頻率1 MHz之相位雜訊為-100.23 dBc/Hz。在供電壓1.4 V下，功率消耗為8.95 mW，輸出功率為 -11.29 dBm。計算優化參數為（FOM）為-176.18 dBc/Hz，晶片面積為0.405 mm2。
二、設計一應用磁耦合變壓器之低功耗雙共振腔壓控振盪器，將交流信號經過磁耦合變壓器之倍率放大效果，提升輸出擺信號，優化相位雜訊特性，使用tsmcTM 90-nm CMOS製程，其振盪頻率為23.99 GHz，可調頻率範圍400 MHz，偏移主頻率1 MHz之相位雜訊為-97.61 dBc/Hz。在供電壓0.7 V下，功率消耗僅1.61 mW，輸出功率為-7.16 dBm。計算優化參數為（FOM）為-183.14 dBc/Hz，晶片面積為0.476 mm2。
三、設計一應用磁耦合變壓器之低功耗正回授考畢茲壓控振盪器，利用正回授技術放大信號擺幅，並設計閘極與源極於相反之相位，使達到轉導提升之效果。使用tsmcTM 0.18-μm CMOS製程，其振盪頻率為22.87 GHz，可調頻率範圍800 MHz，偏移主頻率1 MHz之相位雜訊為-98.83 dBc/Hz。在供電壓1.1 V下，功率消耗僅3.63 mW，輸出功率為-11.34 dBm。計算優化參數為（FOM）為-180.4 dBc/Hz，晶片面積為0.446 mm2
;A CMOS voltage controlled oscillator (VCO) with low power, high output power and good phase noise performance is the most challenging circuit due to low-Q passive component, lossy substrate, and low transconductance of the transistors, especially in microwave-wave frequency. Therefore, the use of low loss and high efficiency transformers is attractive especially in CMOS VCOs. The contents of this thesis are divided into five parts.
Chapter 1 gives the motivation of system applications. Chapter 2 introduces the basic theory and the phase noise mechanisms in voltage controlled oscillator (VCO). Chapter 3 presents several fully-integrated low power VCOs which were fabricated in tsmcTM 0.18-μm and 90-nm CMOS technologies. The focus of this chapter is the research of magnetically coupled transformer. Mgnetically coupled transformers can be exploited to enhance the oscillation amplitude and thus the supply voltage can be reduced for the same phase noise with low power consumption. Therefore, there were three low power and good performance VCOs have been designed by using mgnetically coupled transformers.
In the first design, a low-noise K-band complementary VCO using magnetically coupled transformer was fabricated in 0.18-µm CMOS technology for K-band applications. The start-up condition was more reliable by using the gate inductive peaking technique and magnetically coupled transformers. The measured oscillation central frequency is 23.46 GHz with the tunable frequency range from 23.46 to 24.07 GHz. The phase noise is -100.23 dBc/Hz at 1-MHz offset, and the maximum output power is -11.29 dBm. The total power consumption is 8.95 mW at 1.4-V supply voltage.The FOM is -176.18 dBc/Hz. The chip area, including pads, is 0.405 mm2.
In the second design, an ultra low-power and low-noise VCO using transformer coupled dual LC tanks topology was fabricated in 90-nm CMOS technology. The proposed transformer provides tight coupling factor between two LC tanks that improves the phase noise performance by increasing the output signal swing and waveform symmetry of the VCO. In addition, taking advantage of the tight-coupling transformer, the inductor layout is properly designed to obtain a high Q-factor and a die area comparable to single-inductor VCO. The measured oscillation central frequency is 23.99 GHz with the tunable frequency range from 23.6 to 23.99 GHz. The phase noise is -97.61 dBc/Hz at 1-MHz offset, and the maximum output power is -7.16 dBm. The total power consumption is 1.61 mW at 0.7-V supply voltage.The FOM is -183.14 dBc/Hz. The chip area, including pads, is 0.476 mm2.
In the third disign, a low-power and low-noise Colpitts VCO using trifilar-transformer feedback was fabricated in 0.18-µm CMOS technology. By exploiting the proposed positive-feedback Trifilar network, the required transconductance for the startup oscillation of Colpitts VCO can be reduced, leading to the minimized dc power for sustaining VCO oscillation.The measured oscillation central frequency is 22.83 GHz with the tunable frequency range from 22.8 to 23.6 GHz. The phase noise is -98.83 dBc/Hz at 1-MHz offset, and the maximum output power is -11.34 dBm. The total power consumption is 3.63 mW at 1.1-V supply voltage.The FOM is -180.4 dBc/Hz. The chip area, including pads, is 0.446 mm2.
Finally, the conclusion and future work are given in Chapter 4. |
