矽基板氮化鎵電晶體閘極佈局研究;The study of layout design in GaN HEMTs on Si substrate

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Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/65814

Title:	矽基板氮化鎵電晶體閘極佈局研究;The study of layout design in GaN HEMTs on Si substrate
Authors:	陳政欣;Chen,Cheng-hsin
Contributors:	電機工程學系
Keywords:	元件佈局;氮化鎵;device layout;GaN
Date:	2014-08-19
Issue Date:	2014-10-15 17:10:56 (UTC+8)
Publisher:	國立中央大學
Abstract:	本論文主要針對在低阻值矽（111）基板上進行氮化鋁鎵/氮化鎵電晶體製作與研究，並使用新的閘極佈局方式來提升汲極電流，以降低晶片成本。而電晶體製作採用離子佈植(Ion Implant)作為元件隔絕。論文中，當元件的汲極到源極距離為9 µm，閘極長度為2 µm寬度為104 µm的元件上，單閘極佈局元件的特性為IDSS = 762.7mA/mm, VTH = -7.4 V，而矩陣型佈局元件可以比單閘極佈局元件在相同的元件主動區面積下，得到汲極電流的提升，大約87%的增加量。若在導通電流同約為140 mA時，矩陣型佈局元件可以比單閘極佈局元件在元件主動區結節省約45%的面積。最後，深入探討單閘極元件與矩陣型布局元件間電容與熱阻特性之變化。 ;Two kinds of AlGaN/GaN HEMTs with different device layouts were fabricated and compared. A new matrix layout is proposed to reduce device active area while keeping drain current capability. Compared to device with single finger layout and similar drain current (IDSS = 140 mA), device with matrix layout saves 45% active area. When both of them have the same active area, device with new matrix layout can achieve 1.87 times higher IDSS than device with single finger layout. Finally, the gate capacitances and the thermal resistance of devices with new matrix layout and single finger layout are discussed.
Appears in Collections:	[Graduate Institute of Electrical Engineering] Electronic Thesis & Dissertation

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