CMOS-MEMS電容式加速度計之設計與製作

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Title:	CMOS-MEMS電容式加速度計之設計與製作
Authors:	謝秉勳;Hsieh,Ping-Hsun
Contributors:	機械工程學系
Keywords:	微機電;電容式加速度計;CMOS-MEMS;Accelerometer
Date:	2014-08-29
Issue Date:	2014-10-15 17:20:43 (UTC+8)
Publisher:	國立中央大學
Abstract:	微機電系統(Microelectromechanical Systems, MEMS)結合了微電子技術與機械工程，將傳統的致動器與感測器縮小至微米範圍，並具有低功耗、響應快速等優點，因此在近幾年蓬勃地發展。 MEMS製程無法制式化，對於不同的元件，考量到結構、功能等因素，需設計不同的製程，因此在製作上具有步驟繁複、成本較高等問題，相對MEMS製程，半導體製程技術發展成熟，元件製作精細，尺寸也越來越小，且具有標準化製程，若能整合MEMS與半導體製程技術，更能夠有效提升元件的良率與可靠度，考慮到此整合之必要性，CMOS-MEMS製程技術便由此誕生。本研究中，我們採用TSMC 0.35μm 2P4M製程，將設計元件交由TSMC製造，並結合CIC所提供之後製程，進行結構的釋放。藉由MEMS-CMOS整合技術，我們期望能夠將多種元件，利用標準化的半導體製程製作出來，並借助半導體製程之穩定性，增加元件良率，進一步提升其性質。 ;In this paper, we designed a 2-axis capacitive accelerometer using TSMC 0.35μm 2P4M process and post-process provided by CIC. With standard CMOS process, the reliability of the MEMS device can be increased effectively. The development of MEMS had been strongly increased in recent years due to many advantages such as low power consumption, high response, and small size. The fabricated device is 1172*1172 μm2 in size with 3μm wide oxide comb fingers and 3μm sensing gaps. In CMOS process, 2 layers of polysilicon, 4 layers of metal, and dielectric layers are used to form the structure of the device. By depositing and etching metal layers, electrical paths could be delineated. Vias patterned in dielectric layers are used to electrically connect the different layers of metal. The main structure of accelerometer was then released through polysilicon etching. With vibration of the suspended proof mass, the capacitance between the comb fingers is altered. By using differential capacitance to voltage circuit, capacitance can be measured for given acceleration excitations.
Appears in Collections:	[Graduate Institute of Mechanical Engineering] Electronic Thesis & Dissertation

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