隨著超大型積體電路製程的快速演進，電路繞線的問題也愈趨龐大，不僅讓連線間的延遲 (interconnect delay) 影響到整個電路的時序，天線效應 (antenna effect) 降低製造良率 (manufacturing yield) 的現象也越來越明顯。在實體設計階段 (physical design)，如何最佳化所有連線中最大的延遲，同時避免天線效應的影響，已成為十分重要的課題。 現今已有大量的金屬層分配 (layer assignment) 相關文獻，但其中絕大部分皆沒有考慮每層金屬層之間的相關特性，這將會影響每層金屬層中每條線段 (wire segment) 的容量 (capacity)，以及暴露天線的面積 (antenna expose area)。因此，本篇利用現有的文獻去做改良，使之可以在多層次連線架構 (multi-tier interconnect structure) 下，產生符合天線規則的金屬層分配結果，並且將連線間的延遲資訊帶入目標函式 (object function)，進而優化 (optimize) 連線間的延遲。實驗結果顯示，本篇所提出之改良的方法，可以很明顯地降低天線違反的導線 (antenna violation net)，並且大部分的結果可以在滿足天線規則以及導線擁擠度限制 (wire congestion constraints) 的情況下，優化最大的延遲。 ;With the evolution of VLSI process, the problem size of ASIC routing grows fast. Besides the timing issue from the interconnect delay, the yield loss due to antenna effect is more and more obvious. As a result, simultaneously optimizing the maximum delay and avoiding the antenna effect is an important issue in physical design. Although there are a lot of layer assignment works in the literatures, most of them did not consider the layer dependent characteristics, which induce different routing capacities and antenna expose area in each metal layer. Therefore, based on an existing work, some enhancements are made to obtain an antenna-free assignment under multi-tier interconnect structure in this thesis. The interconnect delay is also considered in the object function to optimize the maximum delay. Experimental results showed that the proposed method can reduce the number of antenna violations significantly. In most of the benchmark circuits, the maximum delay is also optimized while satisfying the antenna rules and wire congestion constraints.
