本論文研究內容以FPGA硬體架構設計與實現DVB-S2內部接收端，包含符碼同步，載波同步，Frame同步以及供給外在接收模組的軟式決策(Soft-Decision)解碼模組。符碼同步採用內插器，以消除時序偏移並進行同步取樣。載波同步則是以固定星座圖計算出相位和頻率偏移，進行回復處理。而Frame同步是經由已知的SOF (Start Of Frame)完成相關器，求出起始位置已截取出正確的Frame範圍，並避免相位的不明確性。而在軟式決定解碼部份，本論文運用了負數旋轉，以對事先計算出的硬式決策(Hard-Decision)邊界，求出與邊界的距離，而得知訊號點的數概似值比(Log Likelihood Ratio, LLR)，以簡化計算的複雜度。;Digital Video Broadcasting - Satellite - Second Generation(DVB-S2) is a digital television broadcast standard that has been designed as a successor for the popular DVB-S system. In comparison with DVB-S, besides QPSK, DVB include enhanced modulation schemes up to 8PSK, 16APSK and 32APSK, which increase of available bitrate over the same satellite transponder bandwidth. Otherwise, it can reduce the phase offset and have a good performance in channel interference.
The reaserch topic of this thesis is on the hardware architecture design and realization of the DVB-S2 inner receiver with FPGA, Including Symbol Synchronization, Carrier Synchronization and Frame Synchronization, and Soft-Decision module which supplys Log likelihood Ratio (LLR) to outer receiver. The Symbol Synchronization uses interpolator to solve timing offset and do the sampling process. The Carrier Synchronization uses the ideal constellation of QPSK, 8PSK, 16APSK and 32APSK to caculate the phase and frequency offset of the input signal.The frame Synchronization uses the SOF(Start of Frame) which is known data to design a correlator, and caculate the beginning of frame. Then, we can catch the frame we need and avoid the ambiguous of phase. About the Soft-Decision, in this thesis I use the complex rotaion to caculate the distance of the boundary of Hard-decision I had caculate in accurate method, and use the distance as the LLR to simplify the caculate.
