具可變倍率可適性相位頻率偵測器之快速鎖定鎖相迴路;A Fast-locking Phase-locked Loop with a Variable Magnification Adaptive Phase Frequency Detector

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Title:	具可變倍率可適性相位頻率偵測器之快速鎖定鎖相迴路;A Fast-locking Phase-locked Loop with a Variable Magnification Adaptive Phase Frequency Detector
Authors:	陳信圭;Chen,Hsin-Kuei
Contributors:	電機工程學系在職專班
Keywords:	快速鎖定;鎖相迴路
Date:	2016-07-26
Issue Date:	2016-10-13 14:31:39 (UTC+8)
Publisher:	國立中央大學
Abstract:	本論文設計一個具快速鎖定的鎖相迴路，電路中之振盪器由四級雙端延遲元件所組成，可提供八個相位振盪頻率為2.5 GHz的輸出訊號，整體電路架構採用了多頻帶的電壓控制振盪器以在製程、電壓及溫度(Process Voltage and Temperature，PVT)漂移的條件下都能追鎖到目標頻率並且降低增益(KVCO)。為了加速追鎖過程則提出了具可變倍率之可適性相位頻率偵測器，使控制電壓能較為迅捷地改變，藉此快速消弭相位差，達到快速鎖定的效果。本論文實現之具可變倍率可適性相位頻率偵測器之快速鎖定鎖相迴路使用CIC 0.18 μm CMOS 1P6M教育製程來實現，電路操作電壓為1.8 V。鎖相迴路的輸入參考時脈為50 MHz，輸出頻率鎖定在2.5 GHz，鎖定時輸出時脈抖動量為6.62 ps (峰對峰值)。鎖定時間為2.59 μs，功率消耗為14.2 mW，晶片面積為660 660 μm2，核心電路部分面積則為380 400 μm2。 ;In this thesis, a fast locking PLL is designed. Its oscillator is composed of 4-stage differential delay cells and can output 8 phase, 2.5 GHz clock signals. The oscillator adopts multi-band architecture to locked the target frequency in process、voltage and temperature drift conditions, and lower the gain of the voltage controlled oscillator (KVCO). The variable magnification adaptive phase frequency detector speed up the tracking so that the control voltage could vary agilely and the phase difference could be eliminated rapidly. This study was implemented by CIC 0.18 μm CMOS 1P6M education process with 1.8 V supply voltage. A 50 MHz clock is used to be input reference clock of PLL, and the output frequency is 2.5 GHz. The period jitter of output frequency is 6.62 ps (peak-to-peak). The locking time of the proposed PLL is 2.59 μs at 2.5 GHz and the power consumption of the PLL is 14.2 mW. The chip area is 660 660 μm2 and the core area is 380 400 μm2.
Appears in Collections:	[Executive Master of Electrical Engineering] Electronic Thesis & Dissertation

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