氧化鉿/氧化鋁/鍺與砷化銦鎵金氧半電容共閘極製程技術與界面缺陷之研究;Characterizations of HfO2/Al2O3/(Ge, InGaAs) MOS Capacitors Fabricated by a Common Gate Stack Process

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Title:	氧化鉿/氧化鋁/鍺與砷化銦鎵金氧半電容共閘極製程技術與界面缺陷之研究;Characterizations of HfO2/Al2O3/(Ge, InGaAs) MOS Capacitors Fabricated by a Common Gate Stack Process
Authors:	李佩佳;Lee,Pei-Chia
Contributors:	電機工程學系
Keywords:	三五族化合物半導體;鍺金氧半電容;砷化銦鎵金氧半電容
Date:	2016-08-29
Issue Date:	2016-10-13 14:37:30 (UTC+8)
Publisher:	國立中央大學
Abstract:	過去幾十年積體電路技術依據莫爾定律持續精進，電晶體的密度與操作頻率不斷地提升，單一晶片之消耗功率亦隨之快速上升，如何在一定的成本之下，持續提升積體電路的性能與降低其消耗功率是國際微電子界眾人所關心的議題。在眾多新材料中，鍺具有高電洞遷移率，被認為最適合取代矽來作為P型電晶體通道的材料，而三五族半導體的高電子遷移率則可以應用在N型通道電晶體。然而，要實現鍺與砷化銦鎵異質整合的互補式金氧半電晶體，目前最需要克服的一項困難是降低介電層與半導體界面存在的高密度缺陷。為此，本論文研究致力於有效降低高介電常數氧化層/鍺與砷化銦鎵界面缺陷密度之方法與金氧半電容之特性分析，並據以了解不同製程影響界面缺陷之機制。本論文中我們首先探討結合化學蝕刻與熱氧化技術進行表面處理後所製作的氧化鉿(4奈米)/氧化鋁(1奈米)/(鍺，砷化銦鎵)電容的特性。實驗結果顯示，在沉積高介電常數氧化層前先進行快速熱氧化步驟，鍺與砷化銦鎵電容室溫下的調變率分別為66 % 和80 %，以電導法萃取界面缺陷密度，靠近價電帶和導電帶約為9.4×1011 eV-1cm-2 和3.9×1011 eV-1cm-2。雖然砷化銦鎵電容特性有所改善，但鍺電容特性的改善程度卻不如預期。為了解決上述缺點，本研究增加氮氣電漿處理鍺與砷化銦鎵熱氧化後的氧化層步驟，從其電容特性中發現，對鍺和砷化銦鎵的氧-半界面來說，此製程能大幅降低能隙中間的界面缺陷密度，同時砷化銦鎵電容的界面缺陷密度最低值出現在導電帶附近，而鍺電容的界面缺陷密度最低值則出現靠近價電帶的地方，其界面缺陷密度分別為3.8×1011 eV-1cm-2及2.3×1011 eV-1cm-2。透過X射線光電子能譜分析氧化層與半導體界面，發現進行快速熱氧化後加入氮氣電漿處理會使鍺的界面出現氮氧化鍺，而砷化銦鎵的界面則產生氮化鋁和氧化鎵的化合物。其中氮氧化鍺能有效地提升電容值以及增加熱穩定性，而砷化銦鎵表面所產生的氧化鎵則形成鈍化層，降低表面材料斷鍵所產生的缺陷，大幅降低界面缺陷密度。此製程技術對於提升鍺與砷化銦鎵金氧半電晶體之閘極調控通道能力以及次臨限斜率等電氣特性是非常重要且實用的。 ;With continuous increase in transistor count and clock frequency of semiconductor integrated circuits over the last 50 years following Moore’s Law, the power density of integrated circuits has reached a level that calls for a revolutionary change in transistor technology. Among the proposed solutions, high hole mobility Ge and high electron mobility InGaAs have been considered to be the most promising channel materials for p-channel and n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs), respectively. However, the native oxides of Ge and InGaAs are typically complex in structure and composition, and causes defect states at oxide-semiconductor interface. This study aims at a surface treatment method to resolve the oxides issue and effectively reduce the density of traps (Dit) at high-κ/(Ge, InGaAs) interface. In addition, a common gate-stack process for Ge and InGaAs devices, consisting of HF cleaning and rapid thermal oxidation (RTO), is developed for fabricating HfO2(4 nm)/Al2O3(1 nm)/(Ge, InGaAs) metal-oxide-semiconductor capacitors (MOSCAPs) by using an atomic layer deposition (ALD) system equipped with a nitrogen plasma source. Typically, the MOSCAPs of Ge and InGaAs prepared by the RTO process show effective capacitance modulation of 66 % and 80 % with interface trap density of 9.4×1011 eV-1cm-2 and 3.9×1011 eV-1cm-2 extracted by conductance method, respectively. Although the capacitance-voltage characteristics of InGaAs MOSCAPs have been improved by the RTO process, the characteristics of Ge ones are not as good as expected. To improve the performance of aforementioned MOSCAPs, an additional surface treatment by nitrogen plasma is performed before high-κ dielectric deposition. Using the RTO process and nitrogen plasma treatment, the Dit at midgap is reduced to 2.3×1011 eV-1cm-2 and 3.8×1011 eV-1cm-2 for Ge and InGaAs MOSCAP, respectively. As evidenced by x-ray photoelectron spectroscopy, there exist GeONx at high-κ/Ge interface and GaOx and AlN at high-κ/InGaAs interface. The GeONx layer is beneficial for the reliability of Ge devices and the GaOx may play a role of passivating surface defects and dangling bonds. The results of this study are well suited for realizing high performance Ge and InGaAs MOSFETs.
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