| 摘要: | 本論文以微型化寬頻六埠網路接收機為主題，發展由微型化六埠網路、寬
頻功率偵測器與類比減法器組成之六埠網路接收機前端電路。為同時達到寬頻與
微型化的效果，首先於積體被動元件(IPD)製程中實現以橋式T 線圈作為基本組
件的微型化寬頻六埠網路，以輸入埠反射損耗大於10dB 定義頻寬，通帶為
1.28GHz~2.81GHz，比例頻寬FBW 為78.5%，電路面積僅為7.780mm×7.938mm，
中心頻率1.95GHz 下之電氣尺寸為0.051λ0×0.052λ0。接續以蕭基二極體(Shottcky
diode)實現中心頻率為1.95GHz ，以輸入反射損耗大於10dB 定義頻寬為
1.06GHz~2.4GHz 的寬頻功率偵測器，並探討改善其靈敏度與轉換效率的設計方
式，再將兩功率偵測器的輸出訊號以類比減法器相減產生解調之I/Q 訊號。本研
究提出兩種減法器設計，以配合不同靈敏度或位元傳輸率之設計考量。最後將減
法器、功率偵測器與寬頻微型化六埠網路晶片，整合於印刷電路板，實現兩種微
型化六埠網路接收機之前端電路，若以10dB 反射損耗定義頻寬，則RF 埠頻寬
為1.4GHz~2.55GHz，比例頻寬FBW=58.97%；LO 埠頻寬為1.35GHz~2.75GHz，
比例頻寬FBW=71.79%，接收機之電路面積為27.71mm×45.72mm，電氣尺寸在
中心頻率1.95GHz 下約為0.18λ0×0.3λ0。本研究測試接收機三種數位調變：QPSK、
16-QAM、64-QAM 下之效能，其可操作頻寬約為1.6GHz~2.4GHz， LO 輸入功
率為0dBm 時，設計Ⅰ在傳輸率1Msps 下，64-QAM 解調靈敏度約為-35dBm，
最高能操作之速度為5Msps 內；設計Ⅱ在傳輸率5Msps 下， 64-QAM 解調靈敏
度約為-15dBm，最高能操作之速度可達20Msps。本研究提出之設計保留六埠網
路架構簡單與寬頻之優點，並利用橋式T 線圈架構達成微型化的設計目標，且能
應用於多種數位調變，未來可進一步整合低雜訊放大器及基頻電路，實現軟體無
線電接收機，並導入次世代手持於線通訊裝置。;This goal of this work is the development of wideband six-port receiver with
compact size. This receiver is composed of six-port network, power detectors and
analog substractors. In order to achieve widewidth band and compact size
simultaneously, bridged-T coil-based six-port network realized by the integrated
passive device (IPD) process is proposed. The measured 10-dB return loss bandwidth
is from 1.28GHz to 2.81GHz and the corresponding fractional bandwidth is 78.5%.
Furthermore, this compact six-port network exhibits a circuit size of only 7.78
mm×7.94 mm, which corresponds to an electrical size of 0.051λ0×0.052λ0 at f0 =
1.95GHz. Next, shottcky diodes are used to implement wideband power detectors with
a center frequency f0=1.95GHz and 10-dB return loss bandwidth from 1.06GHz to
2.4GHz. Parameter studies to improve the sensitivity and conversion efficiency has also
been done. Then, analog subtractors are used to obtain the difference between two
power detector’s outputs to give the demodulated I/Q signal. This work also presents
two subtractor designs for high sensitivity or high bit rate considerations. Lastly, four
power detectors, two analog subtractors, and the six-port network IPD chip are
integrated in a PCB to realize the six-port receiver front-end. The measured 10-dB
return loss bandwidth for the RF port is from 1.4GHz~2.55GHz (FBW = 58.97%) and
that for the LO port is from 1.35GHz~2.75GHz (FBW = 71.79%). The circuit size of
the proposed receiver front end is about 27.71mm×45.72mm, which corresponds to an
electrical size of 0.18λ0×0.3λ0 at f0=1.95GHz. The receiver is tested under three kinds
of modulation scheme, i.e., QPSK, 16-QAM and 64-QAM. The proposed six-port
receiver frond end can cover the frequency band from 1.6GHz to 2.4GHz. For the
designⅠ, under a data rate of 1Msps and a LO power of 0 dBm, the measured RF port
sensitivity for 64-QAM modulation is -35dBm, and the maximal data rate is 5Msps.
III
For the designⅡ under a data rate of 5Msps and a LO power of 0 dBm, the RF port
sensitivity for 64-QAM modulation is -15dBm but a maximal data rate of 20Msps can
be achieved. The proposed receiver front end design maintains the advantages of low
circuit complexity and high bandwidth of the conventional six-port receiver, while the
circuit size is significantly reduced by using bridged-T coils. The proposed receiver can
accommodate multiple modulation schemes. It can be further integrated with a low
noise amplifier, a synthesizer, and baseband circuits to implement a software defined
radio receiver for handheld wireless communication devices. |
