以減少導線負載為目標的效能導向之類比電路繞線方法;On Minimizing Wire Load of Analog Routing for Performance

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題名:	以減少導線負載為目標的效能導向之類比電路繞線方法;On Minimizing Wire Load of Analog Routing for Performance
作者:	紀浩瑜;Chi, Hao-Yu
貢獻者:	電機工程學系
關鍵詞:	類比電路繞線;Analog Routing
日期:	2017-08-11
上傳時間:	2017-10-27 16:12:47 (UTC+8)
出版者:	國立中央大學
摘要:	由於類比電路的敏感性，考量佈局後的非理想效應顯得更為重要。為降低非理想效應對電路效能的影響，類比電路設計大多會採用人工的方式產生佈局，因此需要耗費非常多的時間，雖然使用類比設計自動化工具可以節省設計的工作量，但眾多的佈局限制仍然是類比設計自動化發展的最大難題。除了佈局擺置的問題之外，目前也有一些類比電路繞線的相關文獻，然而大多數的方法還是採取數位電路的繞線模式，也就是在不同的金屬層使用偏好繞線方向的設定完成繞線。這種模式的繞線可以解決導線交錯的問題，但是在水平線與垂直線相連的地方就必須使用導孔來連接，因此會大幅的增加導線中的寄生效應，進而影響了電路的效能。本論文提出一個在繞線階段將線阻最小化的類比設計自動化流程，希望在類比的繞線階段中盡可能地將導線用不換層的方式來完成，而在不換層的同時也需要考慮到線長等因素，使寄生效應降到最低，以確保電路能到達預定的規格。在繞線的過程中，首先針對繞線的路徑做初步的規劃，預估繞線的走向以及降低因為交錯而需要換層的情況發生，接著再將實際的繞線位置尋找出來，最後會用線長以及導孔的電阻值來計算線阻，透過尋找較少的線阻的繞線來做最佳化，而非僅依據線長，如同實驗數據所示，這方法確實可以使寄生效應對電路的影響降低，確保電路在佈局後能夠維持在預定的規格。 ;Because analog circuits are often very sensitive, it is important to consider non-ideal effects in design stage. In order to reduce the impact of non-ideal effects on circuit performance, the layouts of analog circuits are often generated manually, which requires a lot of time. Using EDA tools is a possible way to reduce design efforts, but the complex layout constraints are still a big issue for layout automation. Besides the layout placement problem, there are some literatures on analog routing, too. However, most of the researches on analog layout automation are still using digital routing methodology that sets preferred routing direction for each metal layer. This routing methodology can solve the crossing issue between nets, but an extra via is required to connect the horizontal line and vertical line. Those vias will increase the non-ideal effects on routing nets and influence the circuit performance. This thesis proposes an analog routing flow to minimize the wire resistance at routing stage. In the proposed method, we will try to route each net without changing metal layer and consider the wire length simultaneously to reduce the parasitic effect and keep circuit performance after layout. Frist, this flow will do a preliminary planning about the routing paths and their directions to reduce the layer changing cases due to net crossing. Next, the real routing paths are determined to calculate the wire resistance based on the number of vias and wire length. Instead of wire length, the wire resistance is used in the optimization to find the best path. As shown in the experimental results, this approach is able to reduce the parasitic effects on routing nets and keep the circuit performance after layout.
顯示於類別:	[電機工程研究所] 博碩士論文

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