即時的SIFT特徵點擷取之低記憶體硬體設計;Hardware architecture for real-time SIFT extraction with reduced memory

NCUIR > College of Electrical Engineering & Computer Science > Graduate Institute of Electrical Engineering > Electronic Thesis & Dissertation > Item 987654321/77551

Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/77551

Title:	即時的SIFT特徵點擷取之低記憶體硬體設計;Hardware architecture for real-time SIFT extraction with reduced memory
Authors:	王瑞智;Wang, Rui-Zhi
Contributors:	電機工程學系
Keywords:	尺度不變特徵轉換;SIFT
Date:	2018-05-08
Issue Date:	2018-08-31 14:48:08 (UTC+8)
Publisher:	國立中央大學
Abstract:	在電腦視覺領域中物件匹配及物件辨識一直是廣為研究的題目，其方法主要可透過建立影像中的特徵點再進行特徵點的比對，在眾多的特徵點擷取演算法中，SIFT(Scale invariant feature transform)被認為是效果最好的演算法之一，對於影像縮放、旋轉、變形及光影變化皆能保持不變性，然而其高效及穩定的背後需要付出的是複雜的運算及大量的記憶體空間，這使得SIFT演算法難以達到即時運算（Real-time）。為了達到即時運算及降低記憶體需求，我們在本文中提出了一個新的SIFT硬體架構設計，並對SIFT演算法進行改良。在建構高斯金字塔時我們捨棄原先cascade運算取代為平行運算，雖然增加運算量但可降低暫存記憶體並增加速度；而對於第一組(octave)影像不進行放大取樣，採用較小的尺度空間來模擬高頻的空間頻率；特徵點定位則是選擇改用適當閥值濾除過小的極值，此外整體演算法是基於區塊影像進行運算，透過以上優化能夠大幅降低設計中所需的內部記憶體。我們將硬體架構透過FPGA (Xilinx Artix7)進行驗證，並採用TSMC90nm製程進行實做。實驗結果顯示，在解析度為1280x720的影像中，工作頻率可達152MHz，處理速度可達35.6 frames/s，內部記憶體需求為237Kb。 ;Object matching and identification are the popular research in the field of computer vision. The methods are mainly based on feature matching. In many feature extraction algorithms, SIFT (Scale invariant feature transform) is considered to be one of the best algorithms. It maintains the robustness for image scaling, rotation, deformation, and light changes. However, it require complex calculations and large amounts of memory that makes it difficult to achieve real-time. In order to achieve real-time operations and reduce memory requirements, we propose a new SIFT hardware architecture and improve the SIFT algorithm in this thesis. In the step of constructing Gaussian pyramids, the original cascade operations is substituted by parallel operations. Although it increase the amount of calculations, we can reduce the amount of temporary memory and increase the speed. For the first octave images, we adapt a smaller scale space to simulate the high spatial frequency instead of upsampling image. The step of keypoint localization is replaced by appropriate threshold to filter out the bad extremum. In addition, the overall algorithm is based on segment which can be greatly reduced the internal memory in the design. We verified the hardware architecture on FPGA (Xilinx Artix7) and implemented by TSMC90nm process. Experimental results show that for an image with a resolution of 1280x720, the operating frequency can reach 152 MHz, the processing speed can reach 35.6 frames/s, and the internal memory requirement is 237 Mbits.
Appears in Collections:	[Graduate Institute of Electrical Engineering] Electronic Thesis & Dissertation

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