晶圓圖群集參數分析之C語言加速運算核心;An Accelerated C-Core for Calculating the Cluster Number in Wafer Map Analysis

NCUIR > College of Electrical Engineering & Computer Science > Graduate Institute of Electrical Engineering > Electronic Thesis & Dissertation > Item 987654321/77605

Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/77605

Title:	晶圓圖群集參數分析之C語言加速運算核心;An Accelerated C-Core for Calculating the Cluster Number in Wafer Map Analysis
Authors:	鄭育典;Cheng, Yu-Dian
Contributors:	電機工程學系
Keywords:	迴力棒特徵圖;共同編譯;C語言加速核心
Date:	2018-07-13
Issue Date:	2018-08-31 14:49:45 (UTC+8)
Publisher:	國立中央大學
Abstract:	當晶圓發生問題時可以分成隨機性或系統性的兩種錯誤，本篇論文藉由過去提出之迴力棒特徵圖來分類實際晶圓(WM-811K)發生問題時是由上述的哪一種錯誤所產生。然而隨著科技的進步，晶圓大小以及產出也日益增加，因此我們的模擬也必須因應晶圓尺寸和數量的增加重新作出相對應的結果。這樣的情形造成在建構迴力棒特徵圖時必須模擬更多種類的隨機瑕疵，當隨機瑕疵種類以及晶圓尺寸大小同時增加，會使得先前演算法的模擬時間呈非線性遞增，本論文希望藉由MALAB以及C語言的共同編譯來取代先前只使用MATLAB的演算法。這樣的方法不僅加速建構迴力棒特徵圖以及分類實際晶圓(WM-811K)的模擬，同時也解決了MATLAB中for loop的時間累積效應，使得在模擬尺寸較大或是數量較多的晶圓時可以更快速的得到結果並且不會受到模擬環境的限制。 ;When a problem occurring on a wafer, it can be divided into two kinds of errors, random or systematic. In this study, we use previously proposed boomerang chart to classify the problem of real wafer (WM-811K). However, with the advancement of technology, wafer size and quantity are also increasing. Therefore, our simulation must also re-create corresponding results in response to increasing size and quantity of wafer. This situation results in the need to simulate more kinds of random defects when constructing the boomerang chart. When the random defects and the size of the wafer increase at the same time, the simulation time of the previous algorithm will increase nonlinearly. In this study, we hope to use MALAB and C language co-simulation to replace the previous algorithm in MATLAB. This method not only speeds up the construction of the boomerang chart and the classification of the real wafer (WM-811K), but also solves the time accumulation effect of the for loop in MATLAB, making it possible to simulate bigger or larger numbers of wafers. The results can be obtained more quickly and will not be limited by the simulation environment.
Appears in Collections:	[Graduate Institute of Electrical Engineering] Electronic Thesis & Dissertation

Files in This Item:

File	Description	Size	Format
index.html		0Kb	HTML	163	View/Open

社群 sharing

Loading...