以穿矽孔為技術之 2.5D/3D 積體電路已是一種重要之積體電路設計技術，然而測試與可靠度為 2.5D/3D IC 量產與品質之重要挑戰，因此我們將以總計畫『2.5D/3D 積體電路可測性與可靠性設 計技術』為主軸分為六個子計畫開發解決2.5D/3D IC 測試與可靠度問題。這些子計畫如下：子計 畫一『堆疊式記憶體元件與電路可靠度分析』; 子計畫二『堆疊式記憶體測試與可靠度增強技術』； 子計畫三『堆疊式記憶體控制器層級可靠度增強技術』；子計畫四『2.5D/3D 積體電路處理器可靠 性設計技術』；子計畫五『2.5D/3D 積體電路測試最佳化技術』；及子計畫六『2.5D/3D 積體電路 電源網路可靠性設計技術』。我們將開發從電路層級、RTL 層級、至架構層級之測試與可靠性增 強技術。 無庸置疑地，堆疊式記憶體為2.5D/3D IC 中之重要元件。因此，子計畫二將開發應用於堆疊式記 憶體之有效測試與可靠度增強技術。這些技術包含：1)應用於堆疊式記憶體之自我測試技術；2) 應 用於堆疊式記憶體陣列之自我修復技術；3) 應用於堆疊式記憶體IO 通道之自我修復技術；4) 應 用於堆疊式記憶體之適應性動態錯誤更正碼技術；5) 應用於堆疊式記憶體之混合冗餘位元及錯誤 更正碼技術。 ;Through-silicon-via based 2.5D/3D IC is one important IC design technology. However, testing and reliability issues are two key challenges for the volume production and quality of 2.5D/3D ICs. Therefore, we attempt to develop important techniques for overcoming those two issues under the grand project entitled“Design-for-Testability and -Reliability Techniques for 2.5D/3D ICs” which includes six subprojects. Those subprojects are: subproject 1 entitled “Device and Circuit Reliability Analysis for Stacked Memories”; subproject 2 entitled “Testing and Reliability-Enhancement Techniques for Stacked Memories”; subproject 3 entitled “Controller-Level Reliability-Enhancement Techniques for Stacked Memories”; subproject 4 entitled “Design-for-Reliability Techniques for Processor Cores of 2.5D/3D ICs”; subproject 5 entitled “Test Optimization Techniques for 2.5D/3D ICs”; and subproject 6 entitled ” Design-for-Reliability Techniques for Power/Ground Networks of 2.5D/3D ICs”. We will develop circuit-level, RTL-level, and architecture-level testing and reliability-enhancement techniques for 2.5D/3D ICs. Undoubtedly, stacked memory is one key component in 2.5D/3D ICs. Therefore, subproject 2 will develop effective testing and reliability-enhancement techniques for stacked memories in 2.5D/3D ICs. Those techniques include 1) built-in self-test techniques for stacked memories, 2) built-in self-repair techniques for stack memory arrays, 3) built-in self-repair techniques for IO channels of stacked memories, 4) adaptively dynamic error-correction-code scheme for stacked memories, and 5) hybrid spare bits and error-correction-code techniques for stacked memories.
