應用於高速串列連結之電磁干擾抑制和訊號完整性確保技術設計與實現;Electromagnetic Interference Suppressing and Signal Integrity Ensuring Technology in High-Speed Serial Links

NCUIR > College of Electrical Engineering & Computer Science > Department of Electrical Engineering > Research Project > Item 987654321/78787

Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/78787

Title:	應用於高速串列連結之電磁干擾抑制和訊號完整性確保技術設計與實現;Electromagnetic Interference Suppressing and Signal Integrity Ensuring Technology in High-Speed Serial Links
Authors:	鄭國興
Contributors:	國立中央大學電機工程學系
Keywords:	高速串列連結技術;電磁干擾抑制技術;高速資料傳輸的訊號完整性;展頻時脈電路;連續時間線性等化器;前饋式等化器;決策回饋等化器;資料與時脈回復電路
Date:	2018-12-19
Issue Date:	2018-12-20 13:48:36 (UTC+8)
Publisher:	科技部
Abstract:	隨著積體電路製造技術促進高速數據傳輸的發展，資料傳輸量發展至每秒數兆位元(Gbps)。高速串列連結技術(High-Speed Serial Link Technology)是現今主要數據傳輸技術，亦被廣泛應用在有線收發裝置上。當資料傳輸速率已達每秒數兆位元，發射端的傳輸資料往往伴隨高次諧波，這將導致電磁干擾(Electromagnetic Interference, EMI)，並且嚴重影響周遭其他裝置。因此，具電磁干擾抑制之電源管理電路(EMI-reduction Power IC)及展頻時脈產生器(Spread-Spectrum Clock Generator, SSCG)將扮演重要的角色。此外，訊號完整性(Signal Integrity, SI)的考量也更顯得重要，隨著傳輸速率上升，訊號在通道中的損失越來越嚴重，此外因應傳輸通道的變異性，單一的補償機制已不敷使用。因此，連續時間線性等化器、前饋式等化器、決策回饋等化器和資料與時脈回復電路的關鍵技術開發將具有一定的挑戰性和前瞻性。希望藉由抑制電磁干擾和確保訊號完整性，開發出適用於次世代的高速串列收發器，期盼其可具有低電磁干擾、高速資料傳輸功能及良好功率等效率表現。在第一年的計畫中，將分別以180 nm 和90 nm 製程實現具電磁干擾抑制之電源管理電路和其他不同功能需求之關鍵電路。第二年的計畫中，我們主要重點在於驗證第一年的相關設計，並且將已開發出的技術帶入40 nm 製程。於第三年的計畫中，重點在於進行傳送端和接受端的系統整合。 ;Advance in integrated circuit (IC) fabrication technology facilitates the high-speed transmission of data to be upward evolved into several gigabits per second (Gbps). The high-speed serial link technology is the major technique in modern data transmission. It is widely employed in wireline SerDes applications. As the transmitted data rate has been upgraded into milti-Gbps, the signal of the data launched by the transmitter (TX) accompanies the higher order harmonics. It results in the power-radiated electromagnetic interference (EMI) issue and may stringently affect the other equipment in the vicinity. Thus, an EMI-reduction power IC or a spread-spectrum clock generator (SSCG) plays an important role in such critical building blocks. Moreover, the signal integrity (SI) has to been considered carefully. The higher data transmission has the more channel loss. Furthermore, a simple compensation mechanism is not suitable for various transmission channels. Thus, a continuous time linear equalizer (CTLE), a feed-forward equalizer (FFE), a decision feedback equalizer (DFE) or a clock and data recovery (CDR) becomes a challenge and prospective work. By the EMI suppressing technology and the good SI of high-speed data transmission, the capabilities of low-EMI, high-speed data transmission and good power-efficient are derived. In the first year, we would implement the EMI-reduction power IC and other functional circuits fabricated in 180 nm and 90 nm CMOS process, respectively. In the second year, we would focus on the design of the first year and verify the designed functions. We would extend the schemes into 40 nm CMOS process. Finally, in the third year, we would develop the integrations of TX and receiver (RX).
Relation:	財團法人國家實驗研究院科技政策研究與資訊中心
Appears in Collections:	[Department of Electrical Engineering] Research Project

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