於圖案化鍺模板上選擇性成長之砷化銦鎵鰭式場效電晶體研製;Development of InGaAs Fin Field-Effect Transistors Selectively Grown on Patterned Ge Template

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題名:	於圖案化鍺模板上選擇性成長之砷化銦鎵鰭式場效電晶體研製;Development of InGaAs Fin Field-Effect Transistors Selectively Grown on Patterned Ge Template
作者:	許善軍;Hsu, Shan-Chun
貢獻者:	電機工程學系
關鍵詞:	鰭式場效電晶體;砷化銦鎵;鍺;FinFET;InGaAs;Ge
日期:	2019-01-28
上傳時間:	2019-04-02 15:07:56 (UTC+8)
出版者:	國立中央大學
摘要:	現今矽晶圓廠的生產技術已發展至7奈米節點，電晶體性能已接近物理極限，因此尋找比矽基材料系統更快速且更省電的材料一直以來為半導體界的研究重點。在眾多選項中，具有高電子遷移率的砷化銦鎵與具有高電洞遷移率的鍺，被認為是製作n與p型通道電晶體最具潛力的材料組合之一。因此將兩材料整合於同一矽基板上是未來量產化的關鍵技術之一。本研究率先開發於矽基板上製備鍺模板，再以有機金屬化學蒸氣沉積法(MOCVD)選擇性成長砷化銦鎵於其上，並據以製作鰭式場效電晶體(FinFET)。本論文研究首先以塊材(Bulk)砷化銦鎵磊晶片經蝕刻方式製作鰭式場效電晶體，以驗證及優化製程，作為選擇性磊晶元件之基礎。此研究製備之n型InGaAs FinFET於通道寬度為40奈米、閘極長度為80奈米尺寸時，最大汲極電流密度為250 µA/µm，電流開關比(Ion/Ioff)為104，次臨界擺幅(S.S.)為331 mV/dec，閘極漏電密度約可低於1×10-4 µA/µm。在FinFET製程技術建立後，便分別製作於矽基板上選擇性成長砷化銦鎵鰭式場效電晶體與鍺鳍式場效電晶體。此二元件之通道寬度與閘極長度分別為100 nm/400 nm與80 nm/400 nm，所量得最大汲極電流密度各為118 µA/µm與7.5 µA/µm，電流開關比分別為101與104，次臨界擺幅(S.S.)則為650 mV/dec與90 mV/dec，而閘極漏電密度兩者皆是低於1×10-4 µA/µm。此研究結果已為異質整合三五族與鍺鰭式場效電晶體於矽基板上之構想建立了基礎技術，在優化選擇性成長技術與閘極製程技術後，應可提升汲極電流密度、降低次臨界擺幅、提升電流開關比。 ;Nowadays, Si CMOS manufacturing technology has come to 7 nm technology node and approached its physical limit. New materials that offer high carrier mobility and lead to low power consumption are the focus of research in semiconductor field. For example, III-V compound semiconductor, Among the potential options, InGaAs and Ge, which has high electron and hole mobility, respectively, are one of the best chooses for n-channel and p-channel materials. For the purpose of mass production, heterogenerous integration of InGaAs and Ge on Si substrate monolithicallly is essential. This work demonstrates n-channel fin field-effect transistors (FinFETs) based on InGaAs selectively grown in Ge trench on Si wafers. In this study, FinFETs based on bulk InGaAs/InAlAs epiwafers are fabricated for process development and optimization in the begining. These InGaAs FinFETs exhibit a maximum drain current density of 250 µA/µm, an Ion/Ioff ratio of 104, a subthreshold swing (S.S.) of 331 mV/dec and a gate leakage current below 1×10-4 µA/µm. Devices are then fabricated based on the InGaAs nanostructure selectively grown on patterned Ge templates, which are grown on silicon-on-insulator (SOI) wafers. InGaAs and Ge FinFETs have a channel width and gate length of 100 nm/400 nm and 80 nm/400 nm, respectively. The n-InGaAs FinFETs and Ge FinFETs exhibit an Ion/Ioff ratio of 10 and 104, a maximum drain current density of 118 µA/µm and 7.5 µA/µm, and a subthreshold swing (S.S.) of 650 mV/dec and 90 mV/dec, respectively. The gate leakage current density of both InGaAs and Ge FinFET is below 1×10-4 µA/µm. This work successfully demonstrates the heterogenerous integration of GaAs and Ge FinFETs on Si substrates. Better device performance can be obtained by improving the selective growth and high-k gate-stack processes.
顯示於類別:	[電機工程研究所] 博碩士論文

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