在廣播系統中，很多數位訊號的應用都利用直接錯誤更正碼，它是將多餘的資訊加上原本訊號，以利於被通道干擾之訊號能偵測並更正。在多種錯誤更正碼被發展出來中，以編碼效率及硬體複雜度而言，里德所羅門碼被證實是較好的錯誤更正碼。至今，里德所羅門碼以在廣播系統中被廣泛使用，如在ETSI數位地面電視廣播系統(DVB-T)標準的通道編碼規格，RS(204，188，8) 。 本論文主要是針對數位地面電視廣播系統標準的通道編碼規格來作硬體實現。以Verilog硬體描述語言，並透過Modelsim軟體進行模擬，確認我們的RS(204，188，8)程式可更正錯誤後，在利用合成軟體Synplify合成RTL硬體。 Many digital signaling applications in broadcasting use Forward Error Correction, a technique in which redundant information is added to the signal to allow the receiver to detect and correct errors that may have occurred in transmission. Many different types of code have been devised for this purpose, but Reed-Solomon codes have proved to be a good compromise between efficiency and complexity. Reed-Solomon error correction has several applications in broadcasting, in particular forming part of the specification for the ETSI digital terrestrial television standard, known as DVB-T. In this thesis, we applied the specification for the ETSI digital terrestrial television standard(DVB-T) to realize the hardware implementation of Reed-Solomon decoder. Using Verilog Hardware Description Language and simulating by software “Modelsim” to confirm our program of RS(204,188,8) are fine and can correct errors which result from bad channel. Then, synthesizing logic-RTL by Synplify.
