矽基製程高速寬頻追蹤保持放大器之線性度與改變率研究;Research on Linearity And Droop Rate for Silicon Based High Speed Broadband Track-and-Hold Amplifiers

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题名:	矽基製程高速寬頻追蹤保持放大器之線性度與改變率研究;Research on Linearity And Droop Rate for Silicon Based High Speed Broadband Track-and-Hold Amplifiers
作者:	李承叡;Li, Chang-Ray
贡献者:	電機工程學系
关键词:	矽基製程;追蹤保持放大器;取樣電路;低改變率;高線性度;高速類比互補式金屬氧化物半導體設計;Track-and-Hold Amplifier;High-speed analog CMOS design;Sige;RF and mixed signal IC design;RF front ends sampling circuit;High linearity
日期:	2019-08-21
上传时间:	2019-09-03 16:00:56 (UTC+8)
出版者:	國立中央大學
摘要:	本論文主要探討應用於高速資料轉換系統微波及毫米波頻段高線性度追蹤與保持放大器，並著重於改變率及線性度改良的研究，所提出的設計、研究以及理論計算分析結果將以實際晶片量測結果來做驗證。高速追蹤保持放大器的詳細介紹包含操作原理、重要參數介紹、設計考量、降頻率取樣應用與將在第二章呈現。第三章是使用40 nm CMOS製作的追蹤保持放大器（THA）。設計上採用差動架構的傳統開關電容式（SC）追蹤鎖定（T / H）級，搭配保持模態下的差動饋通消除技術。加入了減輕時脈饋通信號的雜散電晶體，分析其最佳尺寸和電荷注入的電壓誤差分析。時脈緩衝器部分則是使用分佈式放大器，具有寬頻及良好的阻抗匹配特性，輸入高功率弦波使得時脈輸入轉為方波。輸出入緩衝級使用共源級放大器加入主動式電感做頻寬拉升技術，增強追蹤模態頻寬，且不佔用多餘的電路面積。模擬結果顯示，追蹤模式下頻寬為DC~42 GHz，最大無失真動態範圍（SFDR）為46 dBc，平均增益約為 0 dB，直流功耗為217.2 mW，晶片尺寸為0.83× 0.94 mm2。。第四章介紹為DC至34 GHz追蹤保持放大器，採用0.18μm SiGe製程製造。針對數種特性增強技術，包括操作速度提升、線性度提高和解析度增強，將傳統的開關射極隨耦式（SEF）進行分析改良。在開關級加入疊接電晶體，減輕以往面臨的時脈饋通電壓誤差，採用了差動消除技術進一步提高解析度，並分析改良後SEF最佳電晶體尺寸。輸入緩衝級使用源極隨耦器，具有高寬頻的特性，且輸出端可提供合適的電位至SEF開關。輸出緩衝器使用共源級放大器搭配主動式電感執行頻寬拉升技術，進一步增強追蹤模態頻寬。所提出的THA具有34 GHz的追蹤模態頻寬，最大無失真動態範圍（SFDR）為44 dBc，直流功耗為120 mW平均增益約為 0 dB，直流功耗為120 mW，晶片尺寸為1.14× 0.71 mm2。第五章為使用TSMC 0.18 μm SiGe製程所實現DC ~ 40 GHz 主從式追蹤保持放大器，此章節以改良改變率為目標，而做了架構上的修改，將第二章節的追蹤保持（T / H）級為核心後設計主從式追蹤保持放大器。此次設計輸入緩衝器的架構，基本架構為達林頓對，針對THA對高頻寬的特性需求，利用疊接電晶體將達林頓對與輸出端隔離以釋放低通響應，且降低輸出寄生電容。輸出緩衝級參考第四章所使用的源極隨耦器，可以同時兼任前級與後級負載，符合設計上的需求。量測方面，此追蹤保持放大器架構具有40 GHz 的 3-dB輸入頻寬、43.2 dBc無失真動態範圍、平均增益約為 -5 dB，直流功耗為119.4 mW，改變率為4 μV/ps，晶片尺寸為2.135× 0.865 mm2。最後，總結了本論文所提出電路設計架構，並且提出未來設計方向以達到更高速、更寬頻、更好的電路線性度。 ;This thesis mainly discusses the application of high-linearity track and hold amplifiers for high-speed data conversion systems in microwave and millimeter-wave bands, and focuses on the improvement of rate-of-change and linearity. The proposed design, research and theoretical calculations will be verified with on wafer measurement results. The introduction and design considerations of THA includes the operating principle, important parameter descriptions, design considerations, and frequency-down sampling applications will be presented in Chapter 2. The proposed THA with clock buffer is frabricated using TSMC 40 nm CMOS general purpose process in Chapter 3. Compared to the traditional switched-capacitor (SC) track and hold（T / H）stage. A differential cancellation technique is proposed for the track-and-hold stage to reduce the feedthrough during the hold mode. To avoid charge injection, the dummy transistors are adopted in the track-and-hold stage. The clock buffer uses a distributed amplifier with wide bandwidth and good impedance matching, makes the high power input sine wave turn out as a square wave. The input and output buffer use common-source amplifier with active inductor peaking technology to enhance the track-mode bandwidth without taking up extra circuit area. The simulation results show that the measured 3-dB bandwidth of the THA is 42 GHz with small-signal gain of 0 dB. The best SFDR is 46 dBc. The total DC power consumption is 217.2 mW. The chip size is 0.83×0.94 mm2. The proposed THA is frabricated using TSMC 0.18 μm SiGe general purpose process in Chapter 4. Several performance enhancement techniques are investigated including operated speed extension, linearity improvement, and resolution enhancement. Compared to the traditional switch emitter-follower (SEF), a cascode transistor is added to the switch stage to reduce the clock feedthrough voltage error. The differential cancellation technique is used to further improve the resolution and analyze the improved SEF optimal transistor size. Moreover, the common source with active inductor peaking topology is employed to enhance the gain and bandwidth of the THA. The proposed THA has a 3-dB bandwidths of the THA is 34 GHz with small-signal gain of -4.8 dB. The best SFDR is 44 dBc. The total DC power consumption is 120 mW. The chip size is 1.14 ×0.71 mm2. The proposed Master slave THA is frabricated using TSMC 0.18 μm SiGe general purpose process in Chapter 5. To improve the droop rate of the switch stage in Chpater 2, the THA is resimulated and combined as a master slave topology. In order to enhance the operated speed, the modified Darlington-based input buffer is used to release low pass response. The output buffer is designed by using the source follower topology which features low leakage current and broadband output matching. The measured 3-dB bandwidths of the THA is 40 GHz with small-signal gain of -5 dB. The best SFDR is 43.2 dBc. The total DC power consumption is 120 mW, and the droop rate is 4 μV/ps. The size is 2.135 × 0.865 mm2. Lastly, the future work and the conclusions are addressed in Chapter 6
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