在設計深度神經網路（DNN）推論引擎時，會在硬體設計上做不同程度的簡化與修改，以提高能源效率及性能。雖然DNN本質上具有某種程度的容錯能力，但是這些修改都會使得DNN硬體做推論運算時，造成推論正確性下降。如何評估所設計DNN推論引擎的強健性（亦即設計時因運算簡化等造成推論正確率下降程度）是一個重要議題，唯有在設計時可以評估推論正確率，才能有效做硬體簡化及推論正確率的最佳化。另外，DNN推論引擎在使用過程中，會有無可避免的軟錯誤及錯誤發生，這也會造成推論正確率受到影響；更進一步，DNN推論引擎在製造過程中會有瑕疵發生，如何利用DNN本身的容錯能力配合硬體冗餘來有效提升可靠度及良率也是一重要議題。因此本計畫將以開發深度神經網路強健性與可靠性設計技術為目標，主要著重在DNN推論引擎硬體設計時錯誤容忍度的評估方法，以及硬體容錯設計技術。 ;In the design of a deep neural network (DNN) inference engine, typically, we use some computation reduction techniques to boost the energy efficiency and performance of the engine. Although the DNN has the fault resilience capability in nature, those techniques result in the degradation of inference accuracy. How to analyze the robustness, i.e., the influence of inference accuracy caused by the computation reduction techniques, is an important issue. On the other hand, the DNN inference engine might have soft errors or faults during the life time, which results in the degradation of inference accuracy as well. How to take advantage of the self-resilience capability of DNN and hardware redundancy to enhance the reliability and robustness of DNN engines is also an important issue. In this project, therefore, we will develop the analysis platform of robustness and reliability of DNN inference engine and hardware fault tolerance techniques.
