隨著物聯網技術以及第五代通訊技術逐漸純熟以及感測器的技術進步，人工智慧議題再度成為熱門議題，並且逐漸被廣泛應用於自動化工廠、商業數據分析以及自動駕駛技術等領域，人工智慧發展處於數學模型設計及演算法的階段，透過高規格電腦亦或是GPU架構進行演算。由於感測器使用數量上升以及深層神經網路架構的應用，演算的複雜度成指數型上升，功率消耗亦同。相比於大腦生物神經元，電腦運算的體積及單位功耗相當大，因此許多研究朝著類比電路設計之神經元架構邁進。 本文實現一基於生物神經元行為模式之可擴充類比神經元，並採用數位類比轉換器(DAC)及池化(Pooling)電路來實現，然後透過卷積神經網路辨識手寫數字應用驗證其功能。本文採用Current Reference電路將輸入電壓訊號轉換為電流並以Current-steering DAC作為神經網路權重調整功能，透過Q=CV=It將電荷累積至負載電容作為累加器使用來進行卷積運算，最後經由比較器電路進行最大池化運算，得出輸入手寫數字之特徵。 本電路採用台積電0.18μm COMS 1P6M製程，晶片面積約佔0.4255mm^2(包含 I/O PAD)，電源供應電壓為1.8V，整體電路運算輸入為6×10手寫數字之功耗為670.23μW(包含Buffer)，最大操作頻率為4 MHz。輸入0.5V及1V的LSB為103.91nA及198.75nA，INL及DNL皆遠小於0.5LSB，DAC動態範圍約為86.35dB。 ;With the evolution of internet of things (IoT), 5th Generation wireless system and CMOS sensor, artificial intelligence (AI) has again become a hot topic, it is widely used in applications such as automated factories, business data analysis and autonomous driving. The development of AI is at the stage of mathematical model design and algorithm. The complexity of the calculations increases exponentially, as does the power consumption, due to the increase in the number of sensors used and the hidden layer of deep neural network architectures. High-spec computers or GPUs are usually employed to meet the requirement of huge scale of calculations. Compared with brain biological neurons, the volume and unit power consumption of computer calculation are quite large, so many studies are moving towards the neuron architecture of analog circuit design.
This thesis presents a design of extensible analog neuron cell unit based on biological neuron behavior mode. The proposed extensible analog neuron cell unit is composed of a current-steering digital-to-analog converter (DAC) and a pooling circuit. The current reference circuit of current-steering DAC is used to convert the input voltage signal to current, the current steering DAC functions as the neural network weighting to charge the following load capacitor to perform convolution operation, after that, based on the function Q=CV=It, the load capacitor acts as an adder to accumulate charge, and finally the comparator circuit performs the maximum pooling operation. In this dissertation, the proposed extensible analog neuron cell unit is used to obtain the characteristics of input handwritten digits and recognizes handwrite number to demonstrate the circuit function work through convolution neural network.
This circuit is designed in TSMC 0.18μm COMS 1P6M process and the chip area is 0.4255mm^2(including I/O PAD). The power consumption is 670.23μW for 1.8V power supply voltage in calculation an input data of 6×10 handwritten number. The maximum operating frequency is 4 MHz. LSB is 103.91nA and 198.75nA when input is 0.5V and 1V. The INL and DNL are both much smaller than 0.5 LSB and dynamic range is 86.35dB.
