以分段線性表實現基於波動數位濾波器之電路仿真器;Hardware Implementation of WDF-Based Circuit Emulators Using Piecewise Linear Tables

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题名:	以分段線性表實現基於波動數位濾波器之電路仿真器;Hardware Implementation of WDF-Based Circuit Emulators Using Piecewise Linear Tables
作者:	洪思芸;Hong, Si-Yun
贡献者:	電機工程學系
关键词:	數位濾波器;分段線性法;預測法;Wave Digital Filter;Piece-wise linear;Forcasting
日期:	2020-08-17
上传时间:	2020-09-02 18:28:31 (UTC+8)
出版者:	國立中央大學
摘要:	隨著製程技術發展日新月異，超大型積體電路設計愈來愈複雜，單晶片系統( System on Chip , SOC )儼然已成為設計的主流。一個SOC設計當中通常同時包含數位電路與類比電路，所以如何整合與驗證類比/混合訊號(Analog/mixed-signal, AMS)電路將會是一個很大的挑戰，特別是類比電路的部分。數位電路已經有了完整的驗證方法與仿真的平台，然而目前仍缺乏成熟的類比電路仿真器，可以解決混訊驗證的問題。本篇論文中，我們採用波動數位濾波器(Wave Digital Filter, WDF)的原理，將類比電路轉換成對應的數位電路，以達成在FPGA上與數位電路一起模擬的目標。本篇根據之前關於WDF電路仿真的流程，開發了具備動態輸入的混訊電路硬體實現流程，這樣的FPGA硬體實現流程，可以讓整個仿真流程更真實更完整。關於非線性的MOS元件，本論文將原本的查表法，利用分段線性(Piecewise Linear)方法簡化，透過記錄轉折點及斜率，減少了實現表格所需的硬體資源，同時我們也修改了先前的硬體架構，減少FPGA在軟體與硬體間溝通的次數，提高了硬體的吞吐量(Throughput)，加快了仿真的速度。由實驗結果顯示，本篇論文所提出的硬體實現流程可以有效提升波動數位濾波器的硬體仿真效率。 ;With the rapid development of process technology, the design of Very-Large-Scale Integration (VLSI) circuits becomes more and more complex. System-on-Chip (SOC) has become the main stream of VLSI design. Because SOC designs usually consist of both analog and digital circuits, there are big challenges for system integration and verification of Analog/Mixed-Signal (AMS) circuits, especially for analog circuits. Digital circuits already have a complete verification and simulation platform, but there is no mature emulator for analog circuits to solve the problem of mixed-signal verification. In this thesis, we adopt Wave Digital Filter(WDF) theorem to convert analog circuits into corresponding digital circuits. It allows analog circuits to be emulated with digital circuits on the same FPGA. Based on the relevant research of WDF emulation process, this thesis develops the hardware implementation flow of the mixed signal circuits with dynamic inputs. This FPGA implementation flow makes the entire emulation process complete in real applications. About the non-linear MOS components, this thesis uses the Piecewise Linear method to reduce the size of look-up tables dramatically. By recording points and slopes, we reduce the required hardware to implement the tables and still keep the emulation accuracy. We also modify the hardware architecture in previous works to reduce the communication overhead between software and hardware in FPGA. It improves the throughput and accelerates the emulation speed. The experimental results show that the simplified hardware implementation flow can greatly improve the efficiency of analog circuit emulation based on wave digital filters.
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