56/28 Gb/s雙模式高速串列收發器之關鍵技術設計與實現;Design and Implementation of Key Techniques in 56/28 Gb/S Dual-Mode High-Speed Serial Transceiver

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Title:	56/28 Gb/s雙模式高速串列收發器之關鍵技術設計與實現;Design and Implementation of Key Techniques in 56/28 Gb/S Dual-Mode High-Speed Serial Transceiver
Authors:	鄭國興
Contributors:	電機工程學系
Keywords:	高速串列連結技術;低雜訊時脈產生;高速資料傳輸的訊號完整度;鎖相迴路;展頻時脈產生器;連續時間線性等化器;前饋式等化器;決策回饋等化器;資料與時脈回復電路;High-Speed Serial Link Technology;Low-Noise Clock Generation;Signal Integrity of High-Speed Data Transmission;Phase-Locked Loop;Spread-Spectrum Clock Generator;Continuous Time Linear Equalizer;Feed-Forward Equalizer;Decision-Feedback Equalizer;Clock and Data Recovery Circuit
Date:	2020-12-08
Issue Date:	2020-12-09 10:45:53 (UTC+8)
Publisher:	科技部
Abstract:	隨著消費性電子產品的快速發展，資料傳輸速率已發展至每秒數十億位元(Gbps)並往更高的速率邁進。作為大量傳輸資料的關鍵技術，高速串列連結技術(High-Speed Serial Link Technology)被廣泛應用在有線收發裝置上，並發展出四階脈波振幅調變(Four-Level Pulse Amplitude Modulation, PAM4)資料。隨著資料速率的快速提升與新資料格式的提出，衍生出的新議題也必須被審視。首先，操作速度加快，意味著更短的時脈週期與更高百分比的時脈扭曲與抖動，同時，四階脈波振幅調變資料的多重準位也會增加資料邊緣占週期的百分比，並嚴重影響收發器動作。因此，高精準的時脈產生器，鎖相迴路(Phase-Locked Loop, PLL)與展頻時脈產生器(Spread-Spectrum Clock Generator, SSCG)將扮演重要的腳色。此外，傳輸速率的增加也意味著更高的通道衰減，並且四階脈波振幅調變資料的多重準位也壓縮了資料振幅，降低訊號完整度(Signal Integrity, SI)，使得單一的補償機制已不敷使用。因此，連續時間線性等化器(Continuous Time Linear Equalizer, CTLE)、前饋式等化器(Feed-Forward Equalizer, FFE)、決策回饋等化器(Decision-Feedback Equalizer, DFE)和資料與時脈回復電路(Clock and Data Recovery Circuit, CDR)的關鍵技術開發將具有一定的挑戰性與前瞻性。希望藉由確保時脈品質與訊號完整度，開發出適用於四階脈波振幅調變資料的雙模式高速串列收發器。計畫第一年將針對高速串列收發器中關鍵電路進行設計，蒐集分析相關文獻，並透過電路模擬與晶片量測驗證。在第二年的計畫中，將針對發送端與接收端進行初步整合，將第一年的關鍵技術帶入，為最終的高速串列收發器作準備。於第三年的計畫中，重點在於串列收發器中傳送端與接收端之整合優化，將根據前一年的經驗調整系統架構與關鍵電路，實現56/28 Gbps之雙模式高速串列收發器。 ;With the rapid growing of consumer electronics, data transmission rate has evolved to gigabits per second (Gbps) and move toward higher rate. As a key technology for mass data transmission, high-speed serial link technology has been widely used in wireline transceiver and has developed four-level pulse amplitude modulation (PAM4) data. With the rapid increase of data rate and the introduction of new data format, new issues must also be examined. First, the higher operation speed means shorter clock period and higher percentage of clock skew and jitter. At the same time, the multi-level of PAM4 data also increases the percentage of data edge in the period and severely affects the transceiver operation. Therefore, a highly accurate clock generator such as phase-locked loop (PLL) and spread-spectrum clock generator (SSCG) will play an important role in such applications. In addition, the increase in data rate also means the higher channel loss. and the multi-level of PAM4 data also compresses the data amplitude and reduces the signal integrity (SI). As a result, a single compensation mechanism is no longer sufficient. Thus, the development for key technologies of continuous time linear equalizer (CTLE), feed-forward equalizer (FFE), decision-feedback equalizer (DFE) and clock and data recovery circuit (CDR) becomes a challenge and prospective work. By ensuring the clock quality and signal integrity, the dual-mode high-speed transceiver for PAM4 data is developed. The first year will design the key circuits in high-speed serial transceiver, collect and analyze relevant literatures, verify ideas through circuit simulation and chip measurement. In the second year, the preliminary integration for transmitter and receiver will be carried out, and the key technologies of first year will be brought in to prepare for the final high-speed serial transceiver. In the third year, the key point is to optimize the integration of transmitter and receiver in serial transceiver. The system architecture and essential circuit will be adjusted based on the experience of previous year to achieve a 56/28 Gbps dual-mode high-speed serial transceiver.
Relation:	財團法人國家實驗研究院科技政策研究與資訊中心
Appears in Collections:	[Department of Electrical Engineering] Research Project

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