仿生運算於AI晶片之開發與應用：建構通用型類神經網路技術平台與異質晶片整合於圖片辨識之應用(1/3);Developments and Applications of AI chip by Neuromorphic Computing: Construction of General Neuron-Network Technology Platform and Hetero-Integration of AI Chip in Recognition of Images(1/3)

NCUIR > College of Electrical Engineering & Computer Science > Department of Electrical Engineering > Research Project > Item 987654321/84716

Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/84716

Title:	仿生運算於AI晶片之開發與應用：建構通用型類神經網路技術平台與異質晶片整合於圖片辨識之應用(1/3);Developments and Applications of AI chip by Neuromorphic Computing: Construction of General Neuron-Network Technology Platform and Hetero-Integration of AI Chip in Recognition of Images(1/3)
Authors:	謝易叡
Contributors:	電機工程學系
Keywords:	人工智慧;神經網路;突觸;鰭式電晶體;仿生計算;非揮發記憶體;影像及手寫辨識;AI;Neural Network;Synapse;FinFET;Neuromorphic Computing;Nanovolatile Memory;Image and handwriting
Date:	2020-12-08
Issue Date:	2020-12-09 10:46:30 (UTC+8)
Publisher:	科技部
Abstract:	本計畫以類神經網路計算架構為核心，設計與實作通用型類神經網路元件與電路。目前實現類神經網路的三大關鍵部位:突觸、神經元和激發函數皆獨立發展，集成度低。為實現高速低功耗AI晶片，三大功能需繼續融合並提高晶片集成程度。吾人於本計畫提出”FinFET SG-NVM技術平台”，整合突觸、神經元和激發函數於單一元件。FinFET SG-NVM的操作機制是將RRAM下電極與FinFET閘極連接起來，使RRAM電阻改變可調控Vth造成ID改變。為應用FinFET SG-NVM於AI chip中，第一年將設計並製備非揮發性 FinFET SG-NVM元件，將利用NDL的FinFET製程完成前端製程之後再與閘極連接後端金屬製作RRAM。第二年，吾人將利用FinFET SG-NVM實現三大操作，從而成為通用型類神經網路元件，並進一步地製作1kbit NOR-type FinFET SG-NVM MACRO。第三年，吾人提出了FinFET SG-NVM晶片與planar CMOS周邊電路晶片的整合方案並實作異質整合AI晶片，最後此AI晶片將利用手寫英文字母為資料庫驗證整體的訓練與推論的功能。 ;As the Big-data era is coming, algorithms of deep-learning require high accuracy of precise recognition, opening the gate to a new era of AI. Semiconductor industry is the cornerstone of technology innovation, which serves as the core of computing architecture for neuro-network and related circuitries. This project, based on this perspective and with focus on hardware development, will be targeted for the design and implementation of a more efficient, energy-saving, and low-cost devices and circuits for the further development of neuro-networks in the future AI generation. The core functionalities of a neuron-network architecture include Synapses, Neuron, and Activation function. However, these three main functionalities actually develop individually with very low integrations. Therefore, in order to realize high-performance and low power consumption, based on this goal, this project firstly raises a technology platform of FinFET Single-gate Non-volatile Memory, which integrates the core functionalities of synapse, neuron, and activation functions into one device. Moreover, one can design, implement, and prove the functions of neuromorphic computing AI chip on this platform. The operation principle of FinFET SG-NVM is to sense the varying of drain current by modulation of the channel Vth in a FinFET, whose gate electrode is connected to the bottom electrode of RRAM MIM. To apply this FinFET SG-NVM in Neuromorphic computing applications, in the first year of this project, we will design and prepare the FinFET SG-NVM device with capability of linearly tunable conductance. We will utilize the FinFET technology developed by NDL to prepare the FinFET device on the front end of line and then will grow the RRAM MIM on the metal 1 layer with a connection to the gate electrode of the prepared FinFET device. Next, in the second year, we will realize the three main operations in a FinFET SG-NVM unit cell, including (1) linearly tunable conductance(Synapse); (2) accumulation of conductance(neuron); (3) high pass filtering capability by Vth modulation of SG-NVM, imitation of ReLU activation function. Furthermore, we will fabricate a tested 1kbit NOR-type FinFET SG-NVM MACRO. In the last year, we will propose the hetero-integration solution of AI chips by the integration of FinFET SG-NVM MACRO chip and planar-CMOS periphery circuits. That is, we separately prepare FinFET SG-NVM MACRO chip in NDL and design the periphery circuitries in CIC. The latter will be manufactured in foundry. Then we can bond together both the chips on a PCB board through wiring. A hetero-integrated AI chip can be obtained thereby. Finally, we will use this AI chip in the train and inference of the handwriting English alphabet database.
Relation:	財團法人國家實驗研究院科技政策研究與資訊中心
Appears in Collections:	[Department of Electrical Engineering] Research Project

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