在最近的國際半導體技術藍圖中，測試與自動測試設備報告指出艱難的挑戰之一是偵測系統性的瑕疵；良率強化報告同時也指出未來在特徵化，檢測和分析的最重要的關鍵挑戰是非可視性瑕疵和製程變動的識別。本計畫“晶圓圖分析的良率和隨機性的理論探索” 的目標有四，是從基礎分析中，(1) 對空間樣態隨機性給一個特徵值，(2) 計算等效數量的缺陷以表示整合過程的完整性，(3) 探索多元性晶圓圖的缺陷良率公式，以及(4) 找出用於晶圓圖分析的同質性判別式。在學理上，尋求更深入的檢定特徵，從量產晶圓圖中，解析出更多樣的瑕疵樣態和等效瑕疵(非可視性瑕疵和製程變動)的綜合效應，以符合真實世界晶圓圖的樣態。 ;In a recent International Technology Roadmap for Semiconductors (ITRS), the Test and Automatic Test Equipment reports that one of the difficulties of the challenge is to detect systemic defects. In Yield Enhancement, this report also points out that the identification of Non-Visual Defects and Process Variations was set to the most important key challenge in the future. The project "An Academic Exploration on Interpreting the Yield and Randomness for Wafer Map Analysis” aims, from the fundamental analysis, (I) to derive a characteristic value to represent the randomness of the spatial appearance, (II) to calculate an equivalent number of defects to represent the combined process integrity, (III) to explore the defect-yield formula for multipartite wafer map, and (IV) to find the discriminant of homogeneity for wafer map analysis. In terms of academics, it is to seek more in-depth verification features, and to analyze the combined effects of more defect-like states and equivalent defect (non-visual defect and process variation) from the mass production wafer maps.
