使用諧波增強高除數注入鎖定除頻器與四相位考畢子壓控振盪器之研製;High-Division Injection-Locked Frequency Divider with Harmonic Enhancement and Quadrature Colpitts Voltage-Controlled Oscillator

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Title:	使用諧波增強高除數注入鎖定除頻器與四相位考畢子壓控振盪器之研製;High-Division Injection-Locked Frequency Divider with Harmonic Enhancement and Quadrature Colpitts Voltage-Controlled Oscillator
Authors:	林品安;LIN, PIN-AN
Contributors:	電機工程學系
Keywords:	高除數;注入鎖定除頻器;四相位壓控振盪器;High-Division;ILFD;QVCO
Date:	2021-09-09
Issue Date:	2021-12-07 13:13:03 (UTC+8)
Publisher:	國立中央大學
Abstract:	本論文主要探討注入鎖定除頻器與四相位壓控振盪器之研究。在現今的毫米波頻段的收發機系統與雷達中，皆需要一個穩定的本地振盪源，而本地振盪源通常以鎖相迴路來實現。注入鎖定除頻器在鎖相迴路的應用中也相當廣泛，因為注入鎖定除頻器易操作在高頻，使注入鎖定除頻器普遍應用在毫米波頻段的鎖相迴路中的第一級除頻器。　　第二章首先介紹關於應用在鎖相迴路中各個除頻器的種類，並簡述各個除頻器的運作原理、優缺點以及適合的操作頻段。接著介紹注入鎖定除頻器的注入鎖定原理，利用一個RLC振盪器的等效電路圖闡述當有額外的注入訊號時，RLC振盪器的輸出訊號會與注入訊號產生一相位差，並由此推導出注入鎖定頻寬公式。在此章節中介紹高除數除頻器的電路圖，與其理想的電路模型，並由此電路模型簡述運作模式，讓讀者能夠容易理解此高除數除頻器。透過鎖定頻寬分析中的推導公式的過程中可以得知，增強偶次諧波項可使除頻器之鎖定頻寬增強。此章節透過注入鎖定除頻器與電流模式邏輯除頻器的電路架構，並利用TSMC 0.18 μm CMOS的製程成功設計出K頻段注入鎖定除十除頻器。在注入功率為0 dBm時，鎖定頻寬為22到23.2 GHz，鎖定範圍有1.2 GHz相當於5.3 %的比例頻寬，輸出功率在鎖定範圍皆在-13到-14 dBm之間，電路直流功耗為11.4 mW。　　第三章使用電流再利用技術來完成V頻段注入鎖定除頻器之設計，此章節電路架構利用串接兩級注入鎖定除頻器來完成高除數除頻器之設計，最後使用TSMC 90 nm GUTM CMOS來完成此章節的電路設計。在章節一開始首先介紹電流再利用之電路架構，並將其使用在注入鎖定除頻器上。由參考文獻中得知二次注入之增強鎖定頻寬技術，並與之結合至電流再利用架構的注入鎖定頻器。在此章節所提出的電流再利用的二次注入電路架構共有兩種，並與無二次注入的除頻器比較其鎖定頻寬，來驗證所提出的電路架構能有效的增強鎖定頻寬。最後在此次的電路設計裡也使用上一章節的諧波增強技術來進一步加強除頻器之鎖定頻寬。在注入訊號功率為0 dBm時，鎖定頻寬為54.8到60.3 GHz，鎖定範圍為5.5 GHz相當於9.6 %的比例頻寬，輸出功率在鎖定時皆在-13到-14 dBm之間，電路的直流消耗為12.3 mW。　　第四章為K頻段考畢子四相位壓控振盪器。此壓控振盪器利用TSMC 0.18 μm CMOS的製程來完成此章節的電路設計。此章節的壓控振盪器採用考畢子電路架構並利用閘級電感來產生、加強負電阻。此外此章節利用自我注入耦合來達成四相位壓控振盪器之設計。此次電路設計成功實現出在24 GHz附近頻段的輸出訊號，在控制電壓為0 V時，其輸出頻率與輸出功率分別為23.5 GHz, -11 dBm。在控制電壓為1 V時，其輸出頻率與輸出功率分別為22.8 GHz, -10.7 dBm。此次四相位壓控振盪器的可調頻率範圍大約為700 MHz。相位雜訊在控制電壓為0.6 V時有最好的相位雜訊值為-96 dBc/Hz @ 1MHz offset。以其中一個輸出為基準去和其他三個輸出做相位相減，在差動輸出的相位誤差為0.9度。而90度與270度輸出的相位誤差為40到50度。 ;This thesis focuses on the study of injection-locked frequency dividers and quadrature voltage-controlled oscillators (QVCO). A stable local oscillator is necessary for the modern transceiver and radar system up to millimeter-wave bands. The local oscillator can be usually realized using a phase locked loop (PLL). The injection-locked frequency dividers (ILFD) are also employed in the millimeter-wave PLL due to their high speed and low dc power consumption, and the ILFD can be adopted as the first-stage frequency divider in the PLL. 　　Several types of frequency divider for the PLL are introduced in Chapter 2, and they are briefly described with the operation principle and advantages and disadvantages among the presented frequency dividers. Then, the injection locked principle of ILFD is introduced. An injection-locked equation is derived based on an equivalent resistance-inductance-capacitance (RLC) circuit for the oscillator. The phase difference between the oscillator and the injection signal is resulted when the external signal is injected into the oscillator. Thee circuit diagrams and the ideal circuit models of the high-division dividers will be briefly presented with the operation principle. From the locking-range analysis, the locking bandwidth can be enhanced by increasing the even-harmonic term of the oscillator. In this chapter, a 0.18-μm CMOS divide-by-10 ILFD is successfully designed using the harmonic-enhancement technique. With an injection power of 0 dBm, the measured locking range is from 22 to 23.2 GHz with an overall locking range of 1.2 GHz and a 5.3% fractional bandwidth. The measured output power is higher -14 dBm over the locking range. The dc power consumption of the ILFD is 11.4 mW. 　　In Chapter 3, a current-reused technique is employed in a V-band ILFD. The proposed ILFD is composed of two stages of frequency dividers to achieve a high division ratio of 6. The circuit design of the presented ILFD is first presented with some theoretical calculations and simulations. Furthermore, a double-injection technique is also employed in the ILFD circuit design to enhance the locking range, and the ILFD is realized using a TSMC 90-nm CMOS process. As compared with prior art, the proposed ILFD features wide locking range and low dc power. With an input power of 0 dBm, the measured locking range is 54.8 to 60.3 GHz, and the measured output is higher -14 dBm over the locking range. The ILFD has an overall locking range of 5.5 GHz and a 9.6% fractional bandwidth. The DC consumption of the V-band ILFD is 12.3 mW. The measured oscillation frequency is from 22.8 to 23.5 GHz as the controlled voltage is from 0 to 1 V, and the measured output power is higher than -11 dBm over the tuning 　　A K-band Colpitts QVCO is presented in Chapter 4. The presented QVCO is designed using a TSMC 0.18-μm CMOS process. The oscillation core is implemented using Colpitts topology to lower phase noise. Two differential Colpitts oscillators are coupled using a self-injection technique to achieve the quadrature generation. The measured oscillation frequency is from 22.8 to 23.5 GHz as the control voltage is from 0 to 1 V, and the measured output power is higher than -11 dBm over the tuning range. The measured minimum phase noise of the QVCO is -96 dBc/Hz at 1-MHz offset when the control voltage is 0.6 V. The measured phase error is between 40 to 50 degree among the four quadrature outputs.
Appears in Collections:	[Graduate Institute of Electrical Engineering] Electronic Thesis & Dissertation

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